o3-timing-mp.py revision 3200
13134Srdreslin@umich.edu# Copyright (c) 2006 The Regents of The University of Michigan 23134Srdreslin@umich.edu# All rights reserved. 33134Srdreslin@umich.edu# 43134Srdreslin@umich.edu# Redistribution and use in source and binary forms, with or without 53134Srdreslin@umich.edu# modification, are permitted provided that the following conditions are 63134Srdreslin@umich.edu# met: redistributions of source code must retain the above copyright 73134Srdreslin@umich.edu# notice, this list of conditions and the following disclaimer; 83134Srdreslin@umich.edu# redistributions in binary form must reproduce the above copyright 93134Srdreslin@umich.edu# notice, this list of conditions and the following disclaimer in the 103134Srdreslin@umich.edu# documentation and/or other materials provided with the distribution; 113134Srdreslin@umich.edu# neither the name of the copyright holders nor the names of its 123134Srdreslin@umich.edu# contributors may be used to endorse or promote products derived from 133134Srdreslin@umich.edu# this software without specific prior written permission. 143134Srdreslin@umich.edu# 153134Srdreslin@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 163134Srdreslin@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 173134Srdreslin@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 183134Srdreslin@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 193134Srdreslin@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 203134Srdreslin@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 213134Srdreslin@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 223134Srdreslin@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 233134Srdreslin@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 243134Srdreslin@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 253134Srdreslin@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 263134Srdreslin@umich.edu# 273134Srdreslin@umich.edu# Authors: Ron Dreslinski 283134Srdreslin@umich.edu 293134Srdreslin@umich.eduimport m5 303134Srdreslin@umich.edufrom m5.objects import * 313134Srdreslin@umich.edum5.AddToPath('../configs/common') 323134Srdreslin@umich.edufrom FullO3Config import * 333134Srdreslin@umich.edu 343134Srdreslin@umich.edu# -------------------- 353134Srdreslin@umich.edu# Base L1 Cache 363134Srdreslin@umich.edu# ==================== 373134Srdreslin@umich.edu 383134Srdreslin@umich.educlass L1(BaseCache): 393134Srdreslin@umich.edu latency = 1 403134Srdreslin@umich.edu block_size = 64 413134Srdreslin@umich.edu mshrs = 4 423134Srdreslin@umich.edu tgts_per_mshr = 8 433134Srdreslin@umich.edu protocol = CoherenceProtocol(protocol='moesi') 443134Srdreslin@umich.edu 453134Srdreslin@umich.edu# ---------------------- 463134Srdreslin@umich.edu# Base L2 Cache 473134Srdreslin@umich.edu# ---------------------- 483134Srdreslin@umich.edu 493134Srdreslin@umich.educlass L2(BaseCache): 503134Srdreslin@umich.edu block_size = 64 513134Srdreslin@umich.edu latency = 100 523134Srdreslin@umich.edu mshrs = 92 533134Srdreslin@umich.edu tgts_per_mshr = 16 543134Srdreslin@umich.edu write_buffers = 8 553134Srdreslin@umich.edu 563134Srdreslin@umich.edunb_cores = 4 573200Srdreslin@umich.educpus = [ DetailedO3CPU(cpu_id=i) for i in xrange(nb_cores) ] 583134Srdreslin@umich.edu 593134Srdreslin@umich.edu# system simulated 603134Srdreslin@umich.edusystem = System(cpu = cpus, physmem = PhysicalMemory(), membus = 613134Srdreslin@umich.eduBus()) 623134Srdreslin@umich.edu 633134Srdreslin@umich.edu# l2cache & bus 643134Srdreslin@umich.edusystem.toL2Bus = Bus() 653134Srdreslin@umich.edusystem.l2c = L2(size='4MB', assoc=8) 663134Srdreslin@umich.edusystem.l2c.cpu_side = system.toL2Bus.port 673134Srdreslin@umich.edu 683134Srdreslin@umich.edu# connect l2c to membus 693134Srdreslin@umich.edusystem.l2c.mem_side = system.membus.port 703134Srdreslin@umich.edu 713134Srdreslin@umich.edu# add L1 caches 723134Srdreslin@umich.edufor cpu in cpus: 733134Srdreslin@umich.edu cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 743134Srdreslin@umich.edu L1(size = '32kB', assoc = 4)) 753134Srdreslin@umich.edu cpu.mem = cpu.dcache 763134Srdreslin@umich.edu # connect cpu level-1 caches to shared level-2 cache 773134Srdreslin@umich.edu cpu.connectMemPorts(system.toL2Bus) 783134Srdreslin@umich.edu 793134Srdreslin@umich.edu# connect memory to membus 803134Srdreslin@umich.edusystem.physmem.port = system.membus.port 813134Srdreslin@umich.edu 823134Srdreslin@umich.edu 833134Srdreslin@umich.edu# ----------------------- 843134Srdreslin@umich.edu# run simulation 853134Srdreslin@umich.edu# ----------------------- 863134Srdreslin@umich.edu 873134Srdreslin@umich.eduroot = Root( system = system ) 883134Srdreslin@umich.eduroot.system.mem_mode = 'timing' 893200Srdreslin@umich.edu#root.trace.flags="Bus Cache" 903134Srdreslin@umich.edu#root.trace.flags = "BusAddrRanges" 91