memtest-ruby.py revision 9841:69c158420c51
19793Sakash.bagdia@arm.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 27586SAli.Saidi@arm.com# Copyright (c) 2010 Advanced Micro Devices, Inc. 37586SAli.Saidi@arm.com# All rights reserved. 47586SAli.Saidi@arm.com# 57586SAli.Saidi@arm.com# Redistribution and use in source and binary forms, with or without 67586SAli.Saidi@arm.com# modification, are permitted provided that the following conditions are 77586SAli.Saidi@arm.com# met: redistributions of source code must retain the above copyright 87586SAli.Saidi@arm.com# notice, this list of conditions and the following disclaimer; 97586SAli.Saidi@arm.com# redistributions in binary form must reproduce the above copyright 107586SAli.Saidi@arm.com# notice, this list of conditions and the following disclaimer in the 117586SAli.Saidi@arm.com# documentation and/or other materials provided with the distribution; 127586SAli.Saidi@arm.com# neither the name of the copyright holders nor the names of its 133970Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 143005Sstever@eecs.umich.edu# this software without specific prior written permission. 153005Sstever@eecs.umich.edu# 163005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273005Sstever@eecs.umich.edu# 283005Sstever@eecs.umich.edu# Authors: Ron Dreslinski 293005Sstever@eecs.umich.edu 303005Sstever@eecs.umich.eduimport m5 313005Sstever@eecs.umich.edufrom m5.objects import * 323005Sstever@eecs.umich.edufrom m5.defines import buildEnv 333005Sstever@eecs.umich.edufrom m5.util import addToPath 343005Sstever@eecs.umich.eduimport os, optparse, sys 353005Sstever@eecs.umich.edu 363005Sstever@eecs.umich.edu# Get paths we might need 373005Sstever@eecs.umich.educonfig_path = os.path.dirname(os.path.abspath(__file__)) 383005Sstever@eecs.umich.educonfig_root = os.path.dirname(config_path) 393005Sstever@eecs.umich.edum5_root = os.path.dirname(config_root) 403005Sstever@eecs.umich.eduaddToPath(config_root+'/configs/common') 416654Snate@binkert.orgaddToPath(config_root+'/configs/ruby') 426654Snate@binkert.orgaddToPath(config_root+'/configs/topologies') 432889SN/A 442710SN/Aimport Ruby 456654Snate@binkert.orgimport Options 466654Snate@binkert.org 476654Snate@binkert.orgparser = optparse.OptionParser() 485457Ssaidi@eecs.umich.eduOptions.addCommonOptions(parser) 496654Snate@binkert.org 506654Snate@binkert.org# Add the ruby specific and protocol specific options 512934SN/ARuby.define_options(parser) 522549SN/A 532995SN/A(options, args) = parser.parse_args() 543395Shsul@eecs.umich.edu 556981SLisa.Hsu@amd.com# 563448Shsul@eecs.umich.edu# Set the default cache size and associativity to be very small to encourage 578920Snilay@cs.wisc.edu# races between requests and writebacks. 583444Sktlim@umich.edu# 592889SN/Aoptions.l1d_size="256B" 608920Snilay@cs.wisc.eduoptions.l1i_size="256B" 618920Snilay@cs.wisc.eduoptions.l2_size="512B" 623322Shsul@eecs.umich.eduoptions.l3_size="1kB" 632710SN/Aoptions.l1d_assoc=2 642710SN/Aoptions.l1i_assoc=2 652710SN/Aoptions.l2_assoc=2 662710SN/Aoptions.l3_assoc=2 672710SN/Aoptions.ports=32 682710SN/A 693322Shsul@eecs.umich.edu#MAX CORES IS 8 with the fals sharing method 703304Sstever@eecs.umich.edunb_cores = 8 713322Shsul@eecs.umich.edu 723322Shsul@eecs.umich.edu# ruby does not support atomic, functional, or uncacheable accesses 733304Sstever@eecs.umich.educpus = [ MemTest(atomic=False, percent_functional=50, 749653SAndreas.Sandberg@ARM.com percent_uncacheable=0, suppress_func_warnings=True) \ 759653SAndreas.Sandberg@ARM.com for i in xrange(nb_cores) ] 769653SAndreas.Sandberg@ARM.com 779653SAndreas.Sandberg@ARM.com# overwrite options.num_cpus with the nb_cores value 789653SAndreas.Sandberg@ARM.comoptions.num_cpus = nb_cores 799653SAndreas.Sandberg@ARM.com 809653SAndreas.Sandberg@ARM.com# system simulated 813481Shsul@eecs.umich.edusystem = System(cpu = cpus, 823481Shsul@eecs.umich.edu funcmem = SimpleMemory(in_addr_map = False), 832566SN/A physmem = SimpleMemory(null = True), 849665Sandreas.hansson@arm.com funcbus = NoncoherentBus()) 859665Sandreas.hansson@arm.com# Dummy voltage domain for all our clock domains 869665Sandreas.hansson@arm.comsystem.voltage_domain = VoltageDomain() 879665Sandreas.hansson@arm.comsystem.clk_domain = SrcClockDomain(clock = '1GHz', 889665Sandreas.hansson@arm.com voltage_domain = system.voltage_domain) 892995SN/A 903304Sstever@eecs.umich.edu# Create a seperate clock domain for components that should run at 913304Sstever@eecs.umich.edu# CPUs frequency 923304Sstever@eecs.umich.edusystem.cpu_clk_domain = SrcClockDomain(clock = '2GHz', 932995SN/A voltage_domain = system.voltage_domain) 942995SN/A 952995SN/A# All cpus are associated with cpu_clk_domain 962917SN/Afor cpu in cpus: 972995SN/A cpu.clk_domain = system.cpu_clk_domain 988956Sjayneel@cs.wisc.edu 992995SN/Asystem.mem_ranges = AddrRange('256MB') 1008956Sjayneel@cs.wisc.edu 1013304Sstever@eecs.umich.eduRuby.create_system(options, system) 1026135Sgblack@eecs.umich.edu 1036135Sgblack@eecs.umich.edu# Create a separate clock domain for Ruby 1046654Snate@binkert.orgsystem.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 1059665Sandreas.hansson@arm.com voltage_domain = system.voltage_domain) 1066654Snate@binkert.org 1079665Sandreas.hansson@arm.comassert(len(cpus) == len(system.ruby._cpu_ruby_ports)) 1086654Snate@binkert.org 1099665Sandreas.hansson@arm.comfor (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports): 1106654Snate@binkert.org # 1119665Sandreas.hansson@arm.com # Tie the cpu test and functional ports to the ruby cpu ports and 1129665Sandreas.hansson@arm.com # physmem, respectively 1137586SAli.Saidi@arm.com # 1149665Sandreas.hansson@arm.com cpus[i].test = ruby_port.slave 1159665Sandreas.hansson@arm.com cpus[i].functional = system.funcbus.slave 1169665Sandreas.hansson@arm.com 1173819Shsul@eecs.umich.edu # 1189059Snilay@cs.wisc.edu # Since the memtester is incredibly bursty, increase the deadlock 1193819Shsul@eecs.umich.edu # threshold to 1 million cycles 1209793Sakash.bagdia@arm.com # 1219793Sakash.bagdia@arm.com ruby_port.deadlock_threshold = 1000000 1229793Sakash.bagdia@arm.com 1239793Sakash.bagdia@arm.com# connect reference memory to funcbus 1249793Sakash.bagdia@arm.comsystem.funcmem.port = system.funcbus.master 1259790Sakash.bagdia@arm.com 1263873Sbinkertn@umich.edu# ----------------------- 1273873Sbinkertn@umich.edu# run simulation 1283873Sbinkertn@umich.edu# ----------------------- 1293873Sbinkertn@umich.edu 1303873Sbinkertn@umich.eduroot = Root(full_system = False, system = system) 1313873Sbinkertn@umich.eduroot.system.mem_mode = 'timing' 1328659SAli.Saidi@ARM.com 1338659SAli.Saidi@ARM.com# Not much point in this being higher than the L1 latency 1349793Sakash.bagdia@arm.comm5.ticks.setGlobalFrequency('1ns') 1359793Sakash.bagdia@arm.com