memtest-ruby.py revision 9827:f47274776aa0 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2010 Advanced Micro Devices, Inc.
3# All rights reserved.
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14# this software without specific prior written permission.
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16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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27#
28# Authors: Ron Dreslinski
29
30import m5
31from m5.objects import *
32from m5.defines import buildEnv
33from m5.util import addToPath
34import os, optparse, sys
35
36# Get paths we might need
37config_path = os.path.dirname(os.path.abspath(__file__))
38config_root = os.path.dirname(config_path)
39m5_root = os.path.dirname(config_root)
40addToPath(config_root+'/configs/common')
41addToPath(config_root+'/configs/ruby')
42addToPath(config_root+'/configs/topologies')
43
44import Ruby
45import Options
46
47parser = optparse.OptionParser()
48Options.addCommonOptions(parser)
49
50# Add the ruby specific and protocol specific options
51Ruby.define_options(parser)
52
53(options, args) = parser.parse_args()
54
55#
56# Set the default cache size and associativity to be very small to encourage
57# races between requests and writebacks.
58#
59options.l1d_size="256B"
60options.l1i_size="256B"
61options.l2_size="512B"
62options.l3_size="1kB"
63options.l1d_assoc=2
64options.l1i_assoc=2
65options.l2_assoc=2
66options.l3_assoc=2
67
68#MAX CORES IS 8 with the fals sharing method
69nb_cores = 8
70
71# ruby does not support atomic, functional, or uncacheable accesses
72cpus = [ MemTest(atomic=False, percent_functional=50,
73                 percent_uncacheable=0, suppress_func_warnings=True) \
74         for i in xrange(nb_cores) ]
75
76# overwrite options.num_cpus with the nb_cores value
77options.num_cpus = nb_cores
78
79# system simulated
80system = System(cpu = cpus,
81                funcmem = SimpleMemory(in_addr_map = False),
82                physmem = SimpleMemory(null = True),
83                funcbus = NoncoherentBus())
84# Dummy voltage domain for all our clock domains
85system.voltage_domain = VoltageDomain()
86system.clk_domain = SrcClockDomain(clock = '1GHz',
87                                   voltage_domain = system.voltage_domain)
88
89# Create a seperate clock domain for components that should run at
90# CPUs frequency
91system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
92                                       voltage_domain = system.voltage_domain)
93
94# All cpus are associated with cpu_clk_domain
95for cpu in cpus:
96    cpu.clk_domain = system.cpu_clk_domain
97
98system.mem_ranges = AddrRange('256MB')
99
100Ruby.create_system(options, system)
101
102# Create a separate clock domain for Ruby
103system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
104                                        voltage_domain = system.voltage_domain)
105
106assert(len(cpus) == len(system.ruby._cpu_ruby_ports))
107
108for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
109     #
110     # Tie the cpu test and functional ports to the ruby cpu ports and
111     # physmem, respectively
112     #
113     cpus[i].test = ruby_port.slave
114     cpus[i].functional = system.funcbus.slave
115
116     #
117     # Since the memtester is incredibly bursty, increase the deadlock
118     # threshold to 1 million cycles
119     #
120     ruby_port.deadlock_threshold = 1000000
121
122# connect reference memory to funcbus
123system.funcmem.port = system.funcbus.master
124
125# -----------------------
126# run simulation
127# -----------------------
128
129root = Root(full_system = False, system = system)
130root.system.mem_mode = 'timing'
131
132# Not much point in this being higher than the L1 latency
133m5.ticks.setGlobalFrequency('1ns')
134