memtest-ruby.py revision 8802:ef66a9083bc4 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2010 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Ron Dreslinski
29
30import m5
31from m5.objects import *
32from m5.defines import buildEnv
33from m5.util import addToPath
34import os, optparse, sys
35
36# Get paths we might need
37config_path = os.path.dirname(os.path.abspath(__file__))
38config_root = os.path.dirname(config_path)
39m5_root = os.path.dirname(config_root)
40addToPath(config_root+'/configs/common')
41addToPath(config_root+'/configs/ruby')
42
43import Ruby
44
45parser = optparse.OptionParser()
46
47#
48# Add the ruby specific and protocol specific options
49#
50Ruby.define_options(parser)
51
52execfile(os.path.join(config_root, "configs/common", "Options.py"))
53
54(options, args) = parser.parse_args()
55
56#
57# Set the default cache size and associativity to be very small to encourage
58# races between requests and writebacks.
59#
60options.l1d_size="256B"
61options.l1i_size="256B"
62options.l2_size="512B"
63options.l3_size="1kB"
64options.l1d_assoc=2
65options.l1i_assoc=2
66options.l2_assoc=2
67options.l3_assoc=2
68
69#MAX CORES IS 8 with the fals sharing method
70nb_cores = 8
71
72# ruby does not support atomic, functional, or uncacheable accesses
73cpus = [ MemTest(atomic=False, percent_functional=50,
74                 percent_uncacheable=0, suppress_func_warnings=True) \
75         for i in xrange(nb_cores) ]
76
77# overwrite options.num_cpus with the nb_cores value
78options.num_cpus = nb_cores
79
80# system simulated
81system = System(cpu = cpus,
82                funcmem = PhysicalMemory(),
83                physmem = PhysicalMemory())
84
85Ruby.create_system(options, system)
86
87assert(len(cpus) == len(system.ruby._cpu_ruby_ports))
88
89for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
90     #
91     # Tie the cpu test and functional ports to the ruby cpu ports and
92     # physmem, respectively
93     #
94     cpus[i].test = ruby_port.port
95     cpus[i].functional = system.funcmem.port
96
97     #
98     # Since the memtester is incredibly bursty, increase the deadlock
99     # threshold to 1 million cycles
100     #
101     ruby_port.deadlock_threshold = 1000000
102
103     #
104     # Ruby doesn't need the backing image of memory when running with
105     # the tester.
106     #
107     ruby_port.access_phys_mem = False
108
109
110# Connect the system port for loading of binaries etc
111system.system_port = system.ruby._sys_port_proxy.port
112
113# -----------------------
114# run simulation
115# -----------------------
116
117root = Root(full_system = False, system = system)
118root.system.mem_mode = 'timing'
119
120# Not much point in this being higher than the L1 latency
121m5.ticks.setGlobalFrequency('1ns')
122