memtest-ruby.py revision 11670
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2010 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Ron Dreslinski 29 30import m5 31from m5.objects import * 32from m5.defines import buildEnv 33from m5.util import addToPath 34import os, optparse, sys 35 36m5.util.addToPath('../configs/common') 37m5.util.addToPath('../configs/') 38 39from ruby import Ruby 40import Options 41 42parser = optparse.OptionParser() 43Options.addCommonOptions(parser) 44 45# Add the ruby specific and protocol specific options 46Ruby.define_options(parser) 47 48(options, args) = parser.parse_args() 49 50# 51# Set the default cache size and associativity to be very small to encourage 52# races between requests and writebacks. 53# 54options.l1d_size="256B" 55options.l1i_size="256B" 56options.l2_size="512B" 57options.l3_size="1kB" 58options.l1d_assoc=2 59options.l1i_assoc=2 60options.l2_assoc=2 61options.l3_assoc=2 62options.ports=32 63 64#MAX CORES IS 8 with the fals sharing method 65nb_cores = 8 66 67# ruby does not support atomic, functional, or uncacheable accesses 68cpus = [ MemTest(percent_functional=50, 69 percent_uncacheable=0, suppress_func_warnings=True) \ 70 for i in xrange(nb_cores) ] 71 72# overwrite options.num_cpus with the nb_cores value 73options.num_cpus = nb_cores 74 75# system simulated 76system = System(cpu = cpus) 77# Dummy voltage domain for all our clock domains 78system.voltage_domain = VoltageDomain() 79system.clk_domain = SrcClockDomain(clock = '1GHz', 80 voltage_domain = system.voltage_domain) 81 82# Create a seperate clock domain for components that should run at 83# CPUs frequency 84system.cpu_clk_domain = SrcClockDomain(clock = '2GHz', 85 voltage_domain = system.voltage_domain) 86 87# All cpus are associated with cpu_clk_domain 88for cpu in cpus: 89 cpu.clk_domain = system.cpu_clk_domain 90 91system.mem_ranges = AddrRange('256MB') 92 93Ruby.create_system(options, False, system) 94 95# Create a separate clock domain for Ruby 96system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 97 voltage_domain = system.voltage_domain) 98 99assert(len(cpus) == len(system.ruby._cpu_ports)) 100 101for (i, ruby_port) in enumerate(system.ruby._cpu_ports): 102 # 103 # Tie the cpu port to the ruby cpu ports and 104 # physmem, respectively 105 # 106 cpus[i].port = ruby_port.slave 107 108 # 109 # Since the memtester is incredibly bursty, increase the deadlock 110 # threshold to 1 million cycles 111 # 112 ruby_port.deadlock_threshold = 1000000 113 114# ----------------------- 115# run simulation 116# ----------------------- 117 118root = Root(full_system = False, system = system) 119root.system.mem_mode = 'timing' 120 121# Not much point in this being higher than the L1 latency 122m5.ticks.setGlobalFrequency('1ns') 123