memtest-ruby.py revision 8801
16166Ssteve.reinhardt@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan
26928SBrad.Beckmann@amd.com# Copyright (c) 2010 Advanced Micro Devices, Inc.
36166Ssteve.reinhardt@amd.com# All rights reserved.
46166Ssteve.reinhardt@amd.com#
56166Ssteve.reinhardt@amd.com# Redistribution and use in source and binary forms, with or without
66166Ssteve.reinhardt@amd.com# modification, are permitted provided that the following conditions are
76166Ssteve.reinhardt@amd.com# met: redistributions of source code must retain the above copyright
86166Ssteve.reinhardt@amd.com# notice, this list of conditions and the following disclaimer;
96166Ssteve.reinhardt@amd.com# redistributions in binary form must reproduce the above copyright
106166Ssteve.reinhardt@amd.com# notice, this list of conditions and the following disclaimer in the
116166Ssteve.reinhardt@amd.com# documentation and/or other materials provided with the distribution;
126166Ssteve.reinhardt@amd.com# neither the name of the copyright holders nor the names of its
136166Ssteve.reinhardt@amd.com# contributors may be used to endorse or promote products derived from
146166Ssteve.reinhardt@amd.com# this software without specific prior written permission.
156166Ssteve.reinhardt@amd.com#
166166Ssteve.reinhardt@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
176166Ssteve.reinhardt@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
186166Ssteve.reinhardt@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
196166Ssteve.reinhardt@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
206166Ssteve.reinhardt@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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256166Ssteve.reinhardt@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
266166Ssteve.reinhardt@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
276166Ssteve.reinhardt@amd.com#
286166Ssteve.reinhardt@amd.com# Authors: Ron Dreslinski
296166Ssteve.reinhardt@amd.com
306166Ssteve.reinhardt@amd.comimport m5
316166Ssteve.reinhardt@amd.comfrom m5.objects import *
326919SBrad.Beckmann@amd.comfrom m5.defines import buildEnv
336919SBrad.Beckmann@amd.comfrom m5.util import addToPath
346919SBrad.Beckmann@amd.comimport os, optparse, sys
356166Ssteve.reinhardt@amd.com
366919SBrad.Beckmann@amd.comif buildEnv['FULL_SYSTEM']:
376919SBrad.Beckmann@amd.com    panic("This script requires system-emulation mode (*_SE).")
386919SBrad.Beckmann@amd.com
396919SBrad.Beckmann@amd.com# Get paths we might need
406919SBrad.Beckmann@amd.comconfig_path = os.path.dirname(os.path.abspath(__file__))
416919SBrad.Beckmann@amd.comconfig_root = os.path.dirname(config_path)
426919SBrad.Beckmann@amd.comm5_root = os.path.dirname(config_root)
436919SBrad.Beckmann@amd.comaddToPath(config_root+'/configs/common')
446919SBrad.Beckmann@amd.comaddToPath(config_root+'/configs/ruby')
456919SBrad.Beckmann@amd.com
466919SBrad.Beckmann@amd.comimport Ruby
476919SBrad.Beckmann@amd.com
486919SBrad.Beckmann@amd.comparser = optparse.OptionParser()
496919SBrad.Beckmann@amd.com
506919SBrad.Beckmann@amd.com#
517570SBrad.Beckmann@amd.com# Add the ruby specific and protocol specific options
526919SBrad.Beckmann@amd.com#
537570SBrad.Beckmann@amd.comRuby.define_options(parser)
546919SBrad.Beckmann@amd.com
556919SBrad.Beckmann@amd.comexecfile(os.path.join(config_root, "configs/common", "Options.py"))
566919SBrad.Beckmann@amd.com
576919SBrad.Beckmann@amd.com(options, args) = parser.parse_args()
586166Ssteve.reinhardt@amd.com
597570SBrad.Beckmann@amd.com#
607570SBrad.Beckmann@amd.com# Set the default cache size and associativity to be very small to encourage
617570SBrad.Beckmann@amd.com# races between requests and writebacks.
627570SBrad.Beckmann@amd.com#
637570SBrad.Beckmann@amd.comoptions.l1d_size="256B"
647570SBrad.Beckmann@amd.comoptions.l1i_size="256B"
657570SBrad.Beckmann@amd.comoptions.l2_size="512B"
667570SBrad.Beckmann@amd.comoptions.l3_size="1kB"
677570SBrad.Beckmann@amd.comoptions.l1d_assoc=2
687570SBrad.Beckmann@amd.comoptions.l1i_assoc=2
697570SBrad.Beckmann@amd.comoptions.l2_assoc=2
707570SBrad.Beckmann@amd.comoptions.l3_assoc=2
717570SBrad.Beckmann@amd.com
726166Ssteve.reinhardt@amd.com#MAX CORES IS 8 with the fals sharing method
736166Ssteve.reinhardt@amd.comnb_cores = 8
746928SBrad.Beckmann@amd.com
756928SBrad.Beckmann@amd.com# ruby does not support atomic, functional, or uncacheable accesses
768436SBrad.Beckmann@amd.comcpus = [ MemTest(atomic=False, percent_functional=50,
778436SBrad.Beckmann@amd.com                 percent_uncacheable=0, suppress_func_warnings=True) \
786928SBrad.Beckmann@amd.com         for i in xrange(nb_cores) ]
796166Ssteve.reinhardt@amd.com
806919SBrad.Beckmann@amd.com# overwrite options.num_cpus with the nb_cores value
816919SBrad.Beckmann@amd.comoptions.num_cpus = nb_cores
826919SBrad.Beckmann@amd.com
836919SBrad.Beckmann@amd.com# system simulated
846919SBrad.Beckmann@amd.comsystem = System(cpu = cpus,
856919SBrad.Beckmann@amd.com                funcmem = PhysicalMemory(),
866919SBrad.Beckmann@amd.com                physmem = PhysicalMemory())
876289Snate@binkert.org
888436SBrad.Beckmann@amd.comRuby.create_system(options, system)
896166Ssteve.reinhardt@amd.com
908322Ssteve.reinhardt@amd.comassert(len(cpus) == len(system.ruby._cpu_ruby_ports))
916166Ssteve.reinhardt@amd.com
928322Ssteve.reinhardt@amd.comfor (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
936919SBrad.Beckmann@amd.com     #
946919SBrad.Beckmann@amd.com     # Tie the cpu test and functional ports to the ruby cpu ports and
956919SBrad.Beckmann@amd.com     # physmem, respectively
966919SBrad.Beckmann@amd.com     #
976919SBrad.Beckmann@amd.com     cpus[i].test = ruby_port.port
986919SBrad.Beckmann@amd.com     cpus[i].functional = system.funcmem.port
997938SBrad.Beckmann@amd.com
1007938SBrad.Beckmann@amd.com     #
1017938SBrad.Beckmann@amd.com     # Since the memtester is incredibly bursty, increase the deadlock
1027938SBrad.Beckmann@amd.com     # threshold to 1 million cycles
1037938SBrad.Beckmann@amd.com     #
1047938SBrad.Beckmann@amd.com     ruby_port.deadlock_threshold = 1000000
1056166Ssteve.reinhardt@amd.com
1068436SBrad.Beckmann@amd.com     #
1078436SBrad.Beckmann@amd.com     # Ruby doesn't need the backing image of memory when running with
1088436SBrad.Beckmann@amd.com     # the tester.
1098436SBrad.Beckmann@amd.com     #
1108436SBrad.Beckmann@amd.com     ruby_port.access_phys_mem = False
1118436SBrad.Beckmann@amd.com
1128706Sandreas.hansson@arm.com
1138706Sandreas.hansson@arm.com# Connect the system port for loading of binaries etc
1148706Sandreas.hansson@arm.comsystem.system_port = system.ruby._sys_port_proxy.port
1158706Sandreas.hansson@arm.com
1166166Ssteve.reinhardt@amd.com# -----------------------
1176166Ssteve.reinhardt@amd.com# run simulation
1186166Ssteve.reinhardt@amd.com# -----------------------
1196166Ssteve.reinhardt@amd.com
1208801Sgblack@eecs.umich.eduroot = Root(full_system = False, system = system)
1216166Ssteve.reinhardt@amd.comroot.system.mem_mode = 'timing'
1226928SBrad.Beckmann@amd.com
1236928SBrad.Beckmann@amd.com# Not much point in this being higher than the L1 latency
1246928SBrad.Beckmann@amd.comm5.ticks.setGlobalFrequency('1ns')
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