memtest-ruby.py revision 6928
16166Ssteve.reinhardt@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan
26928SBrad.Beckmann@amd.com# Copyright (c) 2010 Advanced Micro Devices, Inc.
36166Ssteve.reinhardt@amd.com# All rights reserved.
46166Ssteve.reinhardt@amd.com#
56166Ssteve.reinhardt@amd.com# Redistribution and use in source and binary forms, with or without
66166Ssteve.reinhardt@amd.com# modification, are permitted provided that the following conditions are
76166Ssteve.reinhardt@amd.com# met: redistributions of source code must retain the above copyright
86166Ssteve.reinhardt@amd.com# notice, this list of conditions and the following disclaimer;
96166Ssteve.reinhardt@amd.com# redistributions in binary form must reproduce the above copyright
106166Ssteve.reinhardt@amd.com# notice, this list of conditions and the following disclaimer in the
116166Ssteve.reinhardt@amd.com# documentation and/or other materials provided with the distribution;
126166Ssteve.reinhardt@amd.com# neither the name of the copyright holders nor the names of its
136166Ssteve.reinhardt@amd.com# contributors may be used to endorse or promote products derived from
146166Ssteve.reinhardt@amd.com# this software without specific prior written permission.
156166Ssteve.reinhardt@amd.com#
166166Ssteve.reinhardt@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
176166Ssteve.reinhardt@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
186166Ssteve.reinhardt@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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266166Ssteve.reinhardt@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
276166Ssteve.reinhardt@amd.com#
286166Ssteve.reinhardt@amd.com# Authors: Ron Dreslinski
296166Ssteve.reinhardt@amd.com
306166Ssteve.reinhardt@amd.comimport m5
316166Ssteve.reinhardt@amd.comfrom m5.objects import *
326919SBrad.Beckmann@amd.comfrom m5.defines import buildEnv
336919SBrad.Beckmann@amd.comfrom m5.util import addToPath
346919SBrad.Beckmann@amd.comimport os, optparse, sys
356166Ssteve.reinhardt@amd.com
366919SBrad.Beckmann@amd.comif buildEnv['FULL_SYSTEM']:
376919SBrad.Beckmann@amd.com    panic("This script requires system-emulation mode (*_SE).")
386919SBrad.Beckmann@amd.com
396919SBrad.Beckmann@amd.com# Get paths we might need
406919SBrad.Beckmann@amd.comconfig_path = os.path.dirname(os.path.abspath(__file__))
416919SBrad.Beckmann@amd.comconfig_root = os.path.dirname(config_path)
426919SBrad.Beckmann@amd.comm5_root = os.path.dirname(config_root)
436919SBrad.Beckmann@amd.comaddToPath(config_root+'/configs/common')
446919SBrad.Beckmann@amd.comaddToPath(config_root+'/configs/ruby')
456919SBrad.Beckmann@amd.com
466919SBrad.Beckmann@amd.comimport Ruby
476919SBrad.Beckmann@amd.com
486919SBrad.Beckmann@amd.comparser = optparse.OptionParser()
496919SBrad.Beckmann@amd.com
506919SBrad.Beckmann@amd.com#
516919SBrad.Beckmann@amd.com# Set the default cache size and associativity to be very small to encourage
526919SBrad.Beckmann@amd.com# races between requests and writebacks.
536919SBrad.Beckmann@amd.com#
546919SBrad.Beckmann@amd.comparser.add_option("--l1d_size", type="string", default="256B")
556919SBrad.Beckmann@amd.comparser.add_option("--l1i_size", type="string", default="256B")
566919SBrad.Beckmann@amd.comparser.add_option("--l2_size", type="string", default="512B")
576919SBrad.Beckmann@amd.comparser.add_option("--l1d_assoc", type="int", default=2)
586919SBrad.Beckmann@amd.comparser.add_option("--l1i_assoc", type="int", default=2)
596919SBrad.Beckmann@amd.comparser.add_option("--l2_assoc", type="int", default=2)
606919SBrad.Beckmann@amd.com
616919SBrad.Beckmann@amd.comexecfile(os.path.join(config_root, "configs/common", "Options.py"))
626919SBrad.Beckmann@amd.com
636919SBrad.Beckmann@amd.com(options, args) = parser.parse_args()
646166Ssteve.reinhardt@amd.com
656166Ssteve.reinhardt@amd.com#MAX CORES IS 8 with the fals sharing method
666166Ssteve.reinhardt@amd.comnb_cores = 8
676928SBrad.Beckmann@amd.com
686928SBrad.Beckmann@amd.com# ruby does not support atomic, functional, or uncacheable accesses
696928SBrad.Beckmann@amd.comcpus = [ MemTest(atomic=False, percent_functional=0, \
706928SBrad.Beckmann@amd.com                 percent_uncacheable=0) \
716928SBrad.Beckmann@amd.com         for i in xrange(nb_cores) ]
726166Ssteve.reinhardt@amd.com
736919SBrad.Beckmann@amd.com# overwrite options.num_cpus with the nb_cores value
746919SBrad.Beckmann@amd.comoptions.num_cpus = nb_cores
756919SBrad.Beckmann@amd.com
766919SBrad.Beckmann@amd.com# system simulated
776919SBrad.Beckmann@amd.comsystem = System(cpu = cpus,
786919SBrad.Beckmann@amd.com                funcmem = PhysicalMemory(),
796919SBrad.Beckmann@amd.com                physmem = PhysicalMemory())
806289Snate@binkert.org
816919SBrad.Beckmann@amd.comsystem.ruby = Ruby.create_system(options, system.physmem)
826166Ssteve.reinhardt@amd.com
836919SBrad.Beckmann@amd.comassert(len(cpus) == len(system.ruby.cpu_ruby_ports))
846166Ssteve.reinhardt@amd.com
856919SBrad.Beckmann@amd.comfor (i, ruby_port) in enumerate(system.ruby.cpu_ruby_ports):
866919SBrad.Beckmann@amd.com     #
876919SBrad.Beckmann@amd.com     # Tie the cpu test and functional ports to the ruby cpu ports and
886919SBrad.Beckmann@amd.com     # physmem, respectively
896919SBrad.Beckmann@amd.com     #
906919SBrad.Beckmann@amd.com     cpus[i].test = ruby_port.port
916919SBrad.Beckmann@amd.com     cpus[i].functional = system.funcmem.port
926166Ssteve.reinhardt@amd.com
936166Ssteve.reinhardt@amd.com# -----------------------
946166Ssteve.reinhardt@amd.com# run simulation
956166Ssteve.reinhardt@amd.com# -----------------------
966166Ssteve.reinhardt@amd.com
976166Ssteve.reinhardt@amd.comroot = Root(system = system)
986166Ssteve.reinhardt@amd.comroot.system.mem_mode = 'timing'
996928SBrad.Beckmann@amd.com
1006928SBrad.Beckmann@amd.com# Not much point in this being higher than the L1 latency
1016928SBrad.Beckmann@amd.comm5.ticks.setGlobalFrequency('1ns')
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