memtest-ruby.py revision 6289
12SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 21762SN/A# All rights reserved. 32SN/A# 42SN/A# Redistribution and use in source and binary forms, with or without 52SN/A# modification, are permitted provided that the following conditions are 62SN/A# met: redistributions of source code must retain the above copyright 72SN/A# notice, this list of conditions and the following disclaimer; 82SN/A# redistributions in binary form must reproduce the above copyright 92SN/A# notice, this list of conditions and the following disclaimer in the 102SN/A# documentation and/or other materials provided with the distribution; 112SN/A# neither the name of the copyright holders nor the names of its 122SN/A# contributors may be used to endorse or promote products derived from 132SN/A# this software without specific prior written permission. 142SN/A# 152SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262SN/A# 272665Ssaidi@eecs.umich.edu# Authors: Ron Dreslinski 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.eduimport m5 302SN/Afrom m5.objects import * 312SN/A 322SN/A 332SN/A#MAX CORES IS 8 with the fals sharing method 342SN/Anb_cores = 8 352147SN/Acpus = [ MemTest() for i in xrange(nb_cores) ] 367678Sgblack@eecs.umich.edu 378229Snate@binkert.orgimport ruby_config 388229Snate@binkert.orgruby_memory = ruby_config.generate("MI_example-homogeneous.rb", nb_cores) 397878Sgblack@eecs.umich.edu 402147SN/A# system simulated 412147SN/Asystem = System(cpu = cpus, funcmem = PhysicalMemory(), 422680Sktlim@umich.edu physmem = ruby_memory, 432132SN/A membus = Bus(clock="500GHz", width=16)) 442147SN/A 455999Snate@binkert.orgfor cpu in cpus: 462147SN/A cpu.test = system.membus.port 472147SN/A cpu.functional = system.funcmem.port 482147SN/A 492147SN/Asystem.physmem.port = system.membus.port 502147SN/A 512147SN/A# ----------------------- 522147SN/A# run simulation 532147SN/A# ----------------------- 542147SN/A 552090SN/Aroot = Root(system = system) 562147SN/Aroot.system.mem_mode = 'timing' 574695Sgblack@eecs.umich.edu