memtest-filter.py revision 3187
16019Shines@cs.fsu.edu# Copyright (c) 2006 The Regents of The University of Michigan 26019Shines@cs.fsu.edu# All rights reserved. 36019Shines@cs.fsu.edu# 46019Shines@cs.fsu.edu# Redistribution and use in source and binary forms, with or without 56019Shines@cs.fsu.edu# modification, are permitted provided that the following conditions are 66019Shines@cs.fsu.edu# met: redistributions of source code must retain the above copyright 76019Shines@cs.fsu.edu# notice, this list of conditions and the following disclaimer; 86019Shines@cs.fsu.edu# redistributions in binary form must reproduce the above copyright 96019Shines@cs.fsu.edu# notice, this list of conditions and the following disclaimer in the 106019Shines@cs.fsu.edu# documentation and/or other materials provided with the distribution; 116019Shines@cs.fsu.edu# neither the name of the copyright holders nor the names of its 126019Shines@cs.fsu.edu# contributors may be used to endorse or promote products derived from 136019Shines@cs.fsu.edu# this software without specific prior written permission. 146019Shines@cs.fsu.edu# 156019Shines@cs.fsu.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 166019Shines@cs.fsu.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 176019Shines@cs.fsu.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 186019Shines@cs.fsu.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 196019Shines@cs.fsu.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 206019Shines@cs.fsu.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 216019Shines@cs.fsu.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 226019Shines@cs.fsu.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 236019Shines@cs.fsu.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 246019Shines@cs.fsu.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 256019Shines@cs.fsu.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 266019Shines@cs.fsu.edu# 276019Shines@cs.fsu.edu# Authors: Ron Dreslinski 286019Shines@cs.fsu.edu 296019Shines@cs.fsu.eduimport m5 306019Shines@cs.fsu.edufrom m5.objects import * 316019Shines@cs.fsu.edu 326019Shines@cs.fsu.edu# -------------------- 336019Shines@cs.fsu.edu# Base L1 Cache 346019Shines@cs.fsu.edu# ==================== 356019Shines@cs.fsu.edu 366242Sgblack@eecs.umich.educlass L1(BaseCache): 376019Shines@cs.fsu.edu latency = 1 386216Snate@binkert.org block_size = 64 396019Shines@cs.fsu.edu mshrs = 4 406019Shines@cs.fsu.edu tgts_per_mshr = 8 416019Shines@cs.fsu.edu protocol = CoherenceProtocol(protocol='moesi') 426019Shines@cs.fsu.edu 436242Sgblack@eecs.umich.edu# ---------------------- 446242Sgblack@eecs.umich.edu# Base L2 Cache 456242Sgblack@eecs.umich.edu# ---------------------- 466242Sgblack@eecs.umich.edu 476242Sgblack@eecs.umich.educlass L2(BaseCache): 486242Sgblack@eecs.umich.edu block_size = 64 496242Sgblack@eecs.umich.edu latency = 100 506242Sgblack@eecs.umich.edu mshrs = 92 516242Sgblack@eecs.umich.edu tgts_per_mshr = 16 526242Sgblack@eecs.umich.edu write_buffers = 8 536242Sgblack@eecs.umich.edu 546242Sgblack@eecs.umich.edunb_cores = 1 556242Sgblack@eecs.umich.educpus = [ MemTest(max_loads=1e12) for i in xrange(nb_cores) ] 566242Sgblack@eecs.umich.edu 576242Sgblack@eecs.umich.edu# system simulated 586242Sgblack@eecs.umich.edusystem = System(cpu = cpus, funcmem = PhysicalMemory(), 596242Sgblack@eecs.umich.edu physmem = PhysicalMemory(), membus = Bus()) 606242Sgblack@eecs.umich.edu 616242Sgblack@eecs.umich.edu# l2cache & bus 626242Sgblack@eecs.umich.edusystem.toL2Bus = Bus() 636242Sgblack@eecs.umich.edusystem.l2c = L2(size='4MB', assoc=8) 646242Sgblack@eecs.umich.edusystem.l2c.cpu_side = system.toL2Bus.port 656242Sgblack@eecs.umich.edu 666242Sgblack@eecs.umich.edu# connect l2c to membus 676242Sgblack@eecs.umich.edusystem.l2c.mem_side = system.membus.port 686242Sgblack@eecs.umich.edu 696019Shines@cs.fsu.edu# add L1 caches 706019Shines@cs.fsu.edufor cpu in cpus: 716019Shines@cs.fsu.edu cpu.l1c = L1(size = '32kB', assoc = 4) 726019Shines@cs.fsu.edu cpu.l1c.cpu_side = cpu.test 736019Shines@cs.fsu.edu cpu.l1c.mem_side = system.toL2Bus.port 746019Shines@cs.fsu.edu system.funcmem.port = cpu.functional 756019Shines@cs.fsu.edu 766019Shines@cs.fsu.edu 776019Shines@cs.fsu.edu# connect memory to membus 786019Shines@cs.fsu.edusystem.physmem.port = system.membus.port 796019Shines@cs.fsu.edu 806019Shines@cs.fsu.edu 816019Shines@cs.fsu.edu# ----------------------- 826019Shines@cs.fsu.edu# run simulation 836019Shines@cs.fsu.edu# ----------------------- 846019Shines@cs.fsu.edu 856019Shines@cs.fsu.eduroot = Root( system = system ) 866019Shines@cs.fsu.eduroot.system.mem_mode = 'timing' 876019Shines@cs.fsu.edu#root.trace.flags="InstExec" 886019Shines@cs.fsu.eduroot.trace.flags="Bus" 896019Shines@cs.fsu.edu