memtest-filter.py revision 11682
112855Sgabeblack@google.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 212855Sgabeblack@google.com# All rights reserved. 312855Sgabeblack@google.com# 412855Sgabeblack@google.com# Redistribution and use in source and binary forms, with or without 512855Sgabeblack@google.com# modification, are permitted provided that the following conditions are 612855Sgabeblack@google.com# met: redistributions of source code must retain the above copyright 712855Sgabeblack@google.com# notice, this list of conditions and the following disclaimer; 812855Sgabeblack@google.com# redistributions in binary form must reproduce the above copyright 912855Sgabeblack@google.com# notice, this list of conditions and the following disclaimer in the 1012855Sgabeblack@google.com# documentation and/or other materials provided with the distribution; 1112855Sgabeblack@google.com# neither the name of the copyright holders nor the names of its 1212855Sgabeblack@google.com# contributors may be used to endorse or promote products derived from 1312855Sgabeblack@google.com# this software without specific prior written permission. 1412855Sgabeblack@google.com# 1512855Sgabeblack@google.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1612855Sgabeblack@google.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1712855Sgabeblack@google.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1812855Sgabeblack@google.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 1912855Sgabeblack@google.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2012855Sgabeblack@google.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2112855Sgabeblack@google.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2212855Sgabeblack@google.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2312855Sgabeblack@google.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2412855Sgabeblack@google.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2512855Sgabeblack@google.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2612855Sgabeblack@google.com# 2712855Sgabeblack@google.com# Authors: Ron Dreslinski 2812855Sgabeblack@google.com 2912855Sgabeblack@google.comimport m5 3012855Sgabeblack@google.comfrom m5.objects import * 3112855Sgabeblack@google.comm5.util.addToPath('../configs/') 3212855Sgabeblack@google.comfrom common.Caches import * 3312855Sgabeblack@google.com 3412855Sgabeblack@google.com#MAX CORES IS 8 with the fals sharing method 3512855Sgabeblack@google.comnb_cores = 8 3612855Sgabeblack@google.comcpus = [ MemTest() for i in xrange(nb_cores) ] 3712855Sgabeblack@google.com 3812855Sgabeblack@google.com# system simulated 3912855Sgabeblack@google.comsystem = System(cpu = cpus, 4012855Sgabeblack@google.com physmem = SimpleMemory(), 4112855Sgabeblack@google.com membus = SystemXBar(width=16, snoop_filter = SnoopFilter())) 4212855Sgabeblack@google.com# Dummy voltage domain for all our clock domains 4312855Sgabeblack@google.comsystem.voltage_domain = VoltageDomain() 4412855Sgabeblack@google.comsystem.clk_domain = SrcClockDomain(clock = '1GHz', 4512855Sgabeblack@google.com voltage_domain = system.voltage_domain) 4612855Sgabeblack@google.com 4712855Sgabeblack@google.com# Create a seperate clock domain for components that should run at 4812855Sgabeblack@google.com# CPUs frequency 4912855Sgabeblack@google.comsystem.cpu_clk_domain = SrcClockDomain(clock = '2GHz', 5012855Sgabeblack@google.com voltage_domain = system.voltage_domain) 5112855Sgabeblack@google.com 5212855Sgabeblack@google.comsystem.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain, 5312855Sgabeblack@google.com snoop_filter = SnoopFilter()) 5412855Sgabeblack@google.comsystem.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8) 5512855Sgabeblack@google.comsystem.l2c.cpu_side = system.toL2Bus.master 5612855Sgabeblack@google.com 5712855Sgabeblack@google.com# connect l2c to membus 5812855Sgabeblack@google.comsystem.l2c.mem_side = system.membus.slave 5912855Sgabeblack@google.com 6012855Sgabeblack@google.com# add L1 caches 6112855Sgabeblack@google.comfor cpu in cpus: 6212855Sgabeblack@google.com # All cpus are associated with cpu_clk_domain 6312855Sgabeblack@google.com cpu.clk_domain = system.cpu_clk_domain 6412855Sgabeblack@google.com cpu.l1c = L1Cache(size = '32kB', assoc = 4) 6512855Sgabeblack@google.com cpu.l1c.cpu_side = cpu.port 6612855Sgabeblack@google.com cpu.l1c.mem_side = system.toL2Bus.slave 6712855Sgabeblack@google.com 6812855Sgabeblack@google.comsystem.system_port = system.membus.slave 6912855Sgabeblack@google.com 7012855Sgabeblack@google.com# connect memory to membus 7112855Sgabeblack@google.comsystem.physmem.port = system.membus.master 7212855Sgabeblack@google.com 7312855Sgabeblack@google.com 7412855Sgabeblack@google.com# ----------------------- 7512855Sgabeblack@google.com# run simulation 7612855Sgabeblack@google.com# ----------------------- 7712855Sgabeblack@google.com 7812855Sgabeblack@google.comroot = Root( full_system = False, system = system ) 7912855Sgabeblack@google.comroot.system.mem_mode = 'timing' 8012855Sgabeblack@google.com