base_config.py revision 9826 
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35#
36# Authors: Andreas Sandberg
37#          Andreas Hansson
38
39from abc import ABCMeta, abstractmethod
40import m5
41from m5.objects import *
42from m5.proxy import *
43m5.util.addToPath('../configs/common')
44import FSConfig
45from Caches import *
46
47_have_kvm_support = 'BaseKvmCPU' in globals()
48
49class BaseSystem(object):
50    """Base system builder.
51
52    This class provides some basic functionality for creating an ARM
53    system with the usual peripherals (caches, GIC, etc.). It allows
54    customization by defining separate methods for different parts of
55    the initialization process.
56    """
57
58    __metaclass__ = ABCMeta
59
60    def __init__(self, mem_mode='timing', mem_class=SimpleMemory,
61                 cpu_class=TimingSimpleCPU, num_cpus=1, checker=False):
62        """Initialize a simple base system.
63
64        Keyword Arguments:
65          mem_mode -- String describing the memory mode (timing or atomic)
66          mem_class -- Memory controller class to use
67          cpu_class -- CPU class to use
68          num_cpus -- Number of CPUs to instantiate
69          checker -- Set to True to add checker CPUs
70        """
71        self.mem_mode = mem_mode
72        self.mem_class = mem_class
73        self.cpu_class = cpu_class
74        self.num_cpus = num_cpus
75        self.checker = checker
76
77    def create_cpus(self, cpu_clk_domain):
78        """Return a list of CPU objects to add to a system."""
79        cpus = [ self.cpu_class(clk_domain = cpu_clk_domain,
80                                cpu_id=i)
81                 for i in range(self.num_cpus) ]
82        if self.checker:
83            for c in cpus:
84                c.addCheckerCpu()
85        return cpus
86
87    def create_caches_private(self, cpu):
88        """Add private caches to a CPU.
89
90        Arguments:
91          cpu -- CPU instance to work on.
92        """
93        cpu.addPrivateSplitL1Caches(L1Cache(size='32kB', assoc=1),
94                                    L1Cache(size='32kB', assoc=4))
95
96    def create_caches_shared(self, system):
97        """Add shared caches to a system.
98
99        Arguments:
100          system -- System to work on.
101
102        Returns:
103          A bus that CPUs should use to connect to the shared cache.
104        """
105        system.toL2Bus = CoherentBus(clk_domain=system.cpu_clk_domain)
106        system.l2c = L2Cache(clk_domain=system.cpu_clk_domain,
107                             size='4MB', assoc=8)
108        system.l2c.cpu_side = system.toL2Bus.master
109        system.l2c.mem_side = system.membus.slave
110        return system.toL2Bus
111
112    def init_cpu(self, system, cpu, sha_bus):
113        """Initialize a CPU.
114
115        Arguments:
116          system -- System to work on.
117          cpu -- CPU to initialize.
118        """
119        if not cpu.switched_out:
120            self.create_caches_private(cpu)
121            cpu.createInterruptController()
122            cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
123                                system.membus)
124
125    def init_kvm(self, system):
126        """Do KVM-specific system initialization.
127
128        Arguments:
129          system -- System to work on.
130        """
131        system.vm = KvmVM()
132
133    def init_system(self, system):
134        """Initialize a system.
135
136        Arguments:
137          system -- System to initialize.
138        """
139        self.create_clk_src(system)
140        system.cpu = self.create_cpus(system.cpu_clk_domain)
141
142        if _have_kvm_support and \
143                any([isinstance(c, BaseKvmCPU) for c in system.cpu]):
144            self.init_kvm(system)
145
146        sha_bus = self.create_caches_shared(system)
147        for cpu in system.cpu:
148            self.init_cpu(system, cpu, sha_bus)
149
150    def create_clk_src(self,system):
151        # Create system clock domain. This provides clock value to every
152        # clocked object that lies beneath it unless explicitly overwritten
153        # by a different clock domain.
154        system.clk_domain = SrcClockDomain(clock = '1GHz')
155
156        # Create a seperate clock domain for components that should
157        # run at CPUs frequency
158        system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
159
160    @abstractmethod
161    def create_system(self):
162        """Create an return an initialized system."""
163        pass
164
165    @abstractmethod
166    def create_root(self):
167        """Create and return a simulation root using the system
168        defined by this class."""
169        pass
170
171class BaseSESystem(BaseSystem):
172    """Basic syscall-emulation builder."""
173
174    def __init__(self, **kwargs):
175        BaseSystem.__init__(self, **kwargs)
176
177    def init_system(self, system):
178        BaseSystem.init_system(self, system)
179
180    def create_system(self):
181        system = System(physmem = self.mem_class(),
182                        membus = CoherentBus(),
183                        mem_mode = self.mem_mode)
184        system.system_port = system.membus.slave
185        system.physmem.port = system.membus.master
186        self.init_system(system)
187        return system
188
189    def create_root(self):
190        system = self.create_system()
191        m5.ticks.setGlobalFrequency('1THz')
192        return Root(full_system=False, system=system)
193
194class BaseSESystemUniprocessor(BaseSESystem):
195    """Basic syscall-emulation builder for uniprocessor systems.
196
197    Note: This class is only really needed to provide backwards
198    compatibility in existing test cases.
199    """
200
201    def __init__(self, **kwargs):
202        BaseSESystem.__init__(self, **kwargs)
203
204    def create_caches_private(self, cpu):
205        # The atomic SE configurations do not use caches
206        if self.mem_mode == "timing":
207            # @todo We might want to revisit these rather enthusiastic L1 sizes
208            cpu.addTwoLevelCacheHierarchy(L1Cache(size='128kB'),
209                                          L1Cache(size='256kB'),
210                                          L2Cache(size='2MB'))
211
212    def create_caches_shared(self, system):
213        return None
214
215class BaseFSSystem(BaseSystem):
216    """Basic full system builder."""
217
218    def __init__(self, **kwargs):
219        BaseSystem.__init__(self, **kwargs)
220
221    def init_system(self, system):
222        BaseSystem.init_system(self, system)
223
224        # create the memory controllers and connect them, stick with
225        # the physmem name to avoid bumping all the reference stats
226        system.physmem = [self.mem_class(range = r,
227                                         conf_table_reported = True)
228                          for r in system.mem_ranges]
229        for i in xrange(len(system.physmem)):
230            system.physmem[i].port = system.membus.master
231
232        # create the iocache, which by default runs at the system clock
233        system.iocache = IOCache(addr_ranges=system.mem_ranges)
234        system.iocache.cpu_side = system.iobus.master
235        system.iocache.mem_side = system.membus.slave
236
237    def create_root(self):
238        system = self.create_system()
239        m5.ticks.setGlobalFrequency('1THz')
240        return Root(full_system=True, system=system)
241
242class BaseFSSystemUniprocessor(BaseFSSystem):
243    """Basic full system builder for uniprocessor systems.
244
245    Note: This class is only really needed to provide backwards
246    compatibility in existing test cases.
247    """
248
249    def __init__(self, **kwargs):
250        BaseFSSystem.__init__(self, **kwargs)
251
252    def create_caches_private(self, cpu):
253        cpu.addTwoLevelCacheHierarchy(L1Cache(size='32kB', assoc=1),
254                                      L1Cache(size='32kB', assoc=4),
255                                      L2Cache(size='4MB', assoc=8))
256
257    def create_caches_shared(self, system):
258        return None
259
260class BaseFSSwitcheroo(BaseFSSystem):
261    """Uniprocessor system prepared for CPU switching"""
262
263    def __init__(self, cpu_classes, **kwargs):
264        BaseFSSystem.__init__(self, **kwargs)
265        self.cpu_classes = tuple(cpu_classes)
266
267    def create_cpus(self, cpu_clk_domain):
268        cpus = [ cclass(clk_domain = cpu_clk_domain,
269                        cpu_id=0,
270                        switched_out=True)
271                 for cclass in self.cpu_classes ]
272        cpus[0].switched_out = False
273        return cpus
274