base_config.py revision 9654 
1# Copyright (c) 2012 ARM Limited
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36# Authors: Andreas Sandberg
37
38from abc import ABCMeta, abstractmethod
39import m5
40from m5.objects import *
41from m5.proxy import *
42m5.util.addToPath('../configs/common')
43import FSConfig
44from Caches import *
45
46_have_kvm_support = 'BaseKvmCPU' in globals()
47
48class BaseSystem(object):
49    """Base system builder.
50
51    This class provides some basic functionality for creating an ARM
52    system with the usual peripherals (caches, GIC, etc.). It allows
53    customization by defining separate methods for different parts of
54    the initialization process.
55    """
56
57    __metaclass__ = ABCMeta
58
59    def __init__(self, mem_mode='timing', cpu_class=TimingSimpleCPU,
60                 num_cpus=1, checker=False):
61        """Initialize a simple ARM system.
62
63        Keyword Arguments:
64          mem_mode -- String describing the memory mode (timing or atomic)
65          cpu_class -- CPU class to use
66          num_cpus -- Number of CPUs to instantiate
67          checker -- Set to True to add checker CPUs
68        """
69        self.mem_mode = mem_mode
70        self.cpu_class = cpu_class
71        self.num_cpus = num_cpus
72        self.checker = checker
73
74    def create_cpus(self):
75        """Return a list of CPU objects to add to a system."""
76        cpus = [ self.cpu_class(cpu_id=i, clock='2GHz')
77                 for i in range(self.num_cpus) ]
78        if self.checker:
79            for c in cpus:
80                c.addCheckerCpu()
81        return cpus
82
83    def create_caches_private(self, cpu):
84        """Add private caches to a CPU.
85
86        Arguments:
87          cpu -- CPU instance to work on.
88        """
89        cpu.addPrivateSplitL1Caches(L1Cache(size='32kB', assoc=1),
90                                    L1Cache(size='32kB', assoc=4))
91
92    def create_caches_shared(self, system):
93        """Add shared caches to a system.
94
95        Arguments:
96          system -- System to work on.
97
98        Returns:
99          A bus that CPUs should use to connect to the shared cache.
100        """
101        system.toL2Bus = CoherentBus(clock='2GHz')
102        system.l2c = L2Cache(clock='2GHz', size='4MB', assoc=8)
103        system.l2c.cpu_side = system.toL2Bus.master
104        system.l2c.mem_side = system.membus.slave
105        return system.toL2Bus
106
107    def init_cpu(self, system, cpu):
108        """Initialize a CPU.
109
110        Arguments:
111          system -- System to work on.
112          cpu -- CPU to initialize.
113        """
114        cpu.createInterruptController()
115
116    def init_kvm(self, system):
117        """Do KVM-specific system initialization.
118
119        Arguments:
120          system -- System to work on.
121        """
122        system.vm = KvmVM()
123
124    def init_system(self, system):
125        """Initialize a system.
126
127        Arguments:
128          system -- System to initialize.
129        """
130        system.cpu = self.create_cpus()
131
132        if _have_kvm_support and \
133                any([isinstance(c, BaseKvmCPU) for c in system.cpu]):
134            self.init_kvm(system)
135
136        sha_bus = self.create_caches_shared(system)
137        for cpu in system.cpu:
138            if not cpu.switched_out:
139                self.create_caches_private(cpu)
140                self.init_cpu(system, cpu)
141                cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
142                                    system.membus)
143            else:
144                self.init_cpu(system, cpu)
145
146    @abstractmethod
147    def create_system(self):
148        """Create an return an initialized system."""
149        pass
150
151    @abstractmethod
152    def create_root(self):
153        """Create and return a simulation root using the system
154        defined by this class."""
155        pass
156
157class BaseFSSystem(BaseSystem):
158    """Basic full system builder."""
159
160    def __init__(self, **kwargs):
161        BaseSystem.__init__(self, **kwargs)
162
163    def init_system(self, system):
164        BaseSystem.init_system(self, system)
165
166        #create the iocache
167        system.iocache = IOCache(clock='1GHz', addr_ranges=system.mem_ranges)
168        system.iocache.cpu_side = system.iobus.master
169        system.iocache.mem_side = system.membus.slave
170
171    def create_root(self):
172        system = self.create_system()
173        m5.ticks.setGlobalFrequency('1THz')
174        return Root(full_system=True, system=system)
175
176class BaseFSSystemUniprocessor(BaseFSSystem):
177    """Basic full system builder for uniprocessor systems.
178
179    Note: This class is only really needed to provide backwards
180    compatibility in existing test cases.
181    """
182
183    def __init__(self, **kwargs):
184        BaseFSSystem.__init__(self, **kwargs)
185
186    def create_caches_private(self, cpu):
187        cpu.addTwoLevelCacheHierarchy(L1Cache(size='32kB', assoc=1),
188                                      L1Cache(size='32kB', assoc=4),
189                                      L2Cache(size='4MB', assoc=8))
190
191    def create_caches_shared(self, system):
192        return None
193
194class BaseFSSwitcheroo(BaseFSSystem):
195    """Uniprocessor system prepared for CPU switching"""
196
197    def __init__(self, cpu_classes, **kwargs):
198        BaseFSSystem.__init__(self, **kwargs)
199        self.cpu_classes = tuple(cpu_classes)
200
201    def create_cpus(self):
202        cpus = [ cclass(cpu_id=0, clock='2GHz', switched_out=True)
203                 for cclass in self.cpu_classes ]
204        cpus[0].switched_out = False
205        return cpus
206