base_config.py revision 11682 
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35#
36# Authors: Andreas Sandberg
37#          Andreas Hansson
38
39from abc import ABCMeta, abstractmethod
40import m5
41from m5.objects import *
42from m5.proxy import *
43m5.util.addToPath('../configs/')
44from common import FSConfig
45from common.Caches import *
46
47_have_kvm_support = 'BaseKvmCPU' in globals()
48
49class BaseSystem(object):
50    """Base system builder.
51
52    This class provides some basic functionality for creating an ARM
53    system with the usual peripherals (caches, GIC, etc.). It allows
54    customization by defining separate methods for different parts of
55    the initialization process.
56    """
57
58    __metaclass__ = ABCMeta
59
60    def __init__(self, mem_mode='timing', mem_class=SimpleMemory,
61                 cpu_class=TimingSimpleCPU, num_cpus=1, num_threads=1,
62                 checker=False,
63                 mem_size=None):
64        """Initialize a simple base system.
65
66        Keyword Arguments:
67          mem_mode -- String describing the memory mode (timing or atomic)
68          mem_class -- Memory controller class to use
69          cpu_class -- CPU class to use
70          num_cpus -- Number of CPUs to instantiate
71          checker -- Set to True to add checker CPUs
72          mem_size -- Override the default memory size
73        """
74        self.mem_mode = mem_mode
75        self.mem_class = mem_class
76        self.cpu_class = cpu_class
77        self.num_cpus = num_cpus
78        self.num_threads = num_threads
79        self.checker = checker
80
81    def create_cpus(self, cpu_clk_domain):
82        """Return a list of CPU objects to add to a system."""
83        cpus = [ self.cpu_class(clk_domain=cpu_clk_domain,
84                                numThreads=self.num_threads,
85                                cpu_id=i)
86                 for i in range(self.num_cpus) ]
87        if self.checker:
88            for c in cpus:
89                c.addCheckerCpu()
90        return cpus
91
92    def create_caches_private(self, cpu):
93        """Add private caches to a CPU.
94
95        Arguments:
96          cpu -- CPU instance to work on.
97        """
98        cpu.addPrivateSplitL1Caches(L1_ICache(size='32kB', assoc=1),
99                                    L1_DCache(size='32kB', assoc=4))
100
101    def create_caches_shared(self, system):
102        """Add shared caches to a system.
103
104        Arguments:
105          system -- System to work on.
106
107        Returns:
108          A bus that CPUs should use to connect to the shared cache.
109        """
110        system.toL2Bus = L2XBar(clk_domain=system.cpu_clk_domain)
111        system.l2c = L2Cache(clk_domain=system.cpu_clk_domain,
112                             size='4MB', assoc=8)
113        system.l2c.cpu_side = system.toL2Bus.master
114        system.l2c.mem_side = system.membus.slave
115        return system.toL2Bus
116
117    def init_cpu(self, system, cpu, sha_bus):
118        """Initialize a CPU.
119
120        Arguments:
121          system -- System to work on.
122          cpu -- CPU to initialize.
123        """
124        if not cpu.switched_out:
125            self.create_caches_private(cpu)
126            cpu.createInterruptController()
127            cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
128                                system.membus)
129
130    def init_kvm(self, system):
131        """Do KVM-specific system initialization.
132
133        Arguments:
134          system -- System to work on.
135        """
136        system.vm = KvmVM()
137
138    def init_system(self, system):
139        """Initialize a system.
140
141        Arguments:
142          system -- System to initialize.
143        """
144        self.create_clk_src(system)
145        system.cpu = self.create_cpus(system.cpu_clk_domain)
146
147        if _have_kvm_support and \
148                any([isinstance(c, BaseKvmCPU) for c in system.cpu]):
149            self.init_kvm(system)
150
151        sha_bus = self.create_caches_shared(system)
152
153        for cpu in system.cpu:
154            self.init_cpu(system, cpu, sha_bus)
155
156    def create_clk_src(self,system):
157        # Create system clock domain. This provides clock value to every
158        # clocked object that lies beneath it unless explicitly overwritten
159        # by a different clock domain.
160        system.voltage_domain = VoltageDomain()
161        system.clk_domain = SrcClockDomain(clock = '1GHz',
162                                           voltage_domain =
163                                           system.voltage_domain)
164
165        # Create a seperate clock domain for components that should
166        # run at CPUs frequency
167        system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
168                                               voltage_domain =
169                                               system.voltage_domain)
170
171    @abstractmethod
172    def create_system(self):
173        """Create an return an initialized system."""
174        pass
175
176    @abstractmethod
177    def create_root(self):
178        """Create and return a simulation root using the system
179        defined by this class."""
180        pass
181
182class BaseSESystem(BaseSystem):
183    """Basic syscall-emulation builder."""
184
185    def __init__(self, **kwargs):
186        BaseSystem.__init__(self, **kwargs)
187
188    def init_system(self, system):
189        BaseSystem.init_system(self, system)
190
191    def create_system(self):
192        system = System(physmem = self.mem_class(),
193                        membus = SystemXBar(),
194                        mem_mode = self.mem_mode,
195                        multi_thread = (self.num_threads > 1))
196        system.system_port = system.membus.slave
197        system.physmem.port = system.membus.master
198        self.init_system(system)
199        return system
200
201    def create_root(self):
202        system = self.create_system()
203        m5.ticks.setGlobalFrequency('1THz')
204        return Root(full_system=False, system=system)
205
206class BaseSESystemUniprocessor(BaseSESystem):
207    """Basic syscall-emulation builder for uniprocessor systems.
208
209    Note: This class is only really needed to provide backwards
210    compatibility in existing test cases.
211    """
212
213    def __init__(self, **kwargs):
214        BaseSESystem.__init__(self, **kwargs)
215
216    def create_caches_private(self, cpu):
217        # The atomic SE configurations do not use caches
218        if self.mem_mode == "timing":
219            # @todo We might want to revisit these rather enthusiastic L1 sizes
220            cpu.addTwoLevelCacheHierarchy(L1_ICache(size='128kB'),
221                                          L1_DCache(size='256kB'),
222                                          L2Cache(size='2MB'))
223
224    def create_caches_shared(self, system):
225        return None
226
227class BaseFSSystem(BaseSystem):
228    """Basic full system builder."""
229
230    def __init__(self, **kwargs):
231        BaseSystem.__init__(self, **kwargs)
232
233    def init_system(self, system):
234        BaseSystem.init_system(self, system)
235
236        # create the memory controllers and connect them, stick with
237        # the physmem name to avoid bumping all the reference stats
238        system.physmem = [self.mem_class(range = r)
239                          for r in system.mem_ranges]
240        for i in xrange(len(system.physmem)):
241            system.physmem[i].port = system.membus.master
242
243        # create the iocache, which by default runs at the system clock
244        system.iocache = IOCache(addr_ranges=system.mem_ranges)
245        system.iocache.cpu_side = system.iobus.master
246        system.iocache.mem_side = system.membus.slave
247
248    def create_root(self):
249        system = self.create_system()
250        m5.ticks.setGlobalFrequency('1THz')
251        return Root(full_system=True, system=system)
252
253class BaseFSSystemUniprocessor(BaseFSSystem):
254    """Basic full system builder for uniprocessor systems.
255
256    Note: This class is only really needed to provide backwards
257    compatibility in existing test cases.
258    """
259
260    def __init__(self, **kwargs):
261        BaseFSSystem.__init__(self, **kwargs)
262
263    def create_caches_private(self, cpu):
264        cpu.addTwoLevelCacheHierarchy(L1_ICache(size='32kB', assoc=1),
265                                      L1_DCache(size='32kB', assoc=4),
266                                      L2Cache(size='4MB', assoc=8))
267
268    def create_caches_shared(self, system):
269        return None
270
271class BaseFSSwitcheroo(BaseFSSystem):
272    """Uniprocessor system prepared for CPU switching"""
273
274    def __init__(self, cpu_classes, **kwargs):
275        BaseFSSystem.__init__(self, **kwargs)
276        self.cpu_classes = tuple(cpu_classes)
277
278    def create_cpus(self, cpu_clk_domain):
279        cpus = [ cclass(clk_domain = cpu_clk_domain,
280                        cpu_id=0,
281                        switched_out=True)
282                 for cclass in self.cpu_classes ]
283        cpus[0].switched_out = False
284        return cpus
285