base_config.py revision 9674 
1# Copyright (c) 2012 ARM Limited
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36# Authors: Andreas Sandberg
37
38from abc import ABCMeta, abstractmethod
39import m5
40from m5.objects import *
41from m5.proxy import *
42m5.util.addToPath('../configs/common')
43import FSConfig
44from Caches import *
45
46_have_kvm_support = 'BaseKvmCPU' in globals()
47
48class BaseSystem(object):
49    """Base system builder.
50
51    This class provides some basic functionality for creating an ARM
52    system with the usual peripherals (caches, GIC, etc.). It allows
53    customization by defining separate methods for different parts of
54    the initialization process.
55    """
56
57    __metaclass__ = ABCMeta
58
59    def __init__(self, mem_mode='timing', cpu_class=TimingSimpleCPU,
60                 num_cpus=1, checker=False):
61        """Initialize a simple ARM system.
62
63        Keyword Arguments:
64          mem_mode -- String describing the memory mode (timing or atomic)
65          cpu_class -- CPU class to use
66          num_cpus -- Number of CPUs to instantiate
67          checker -- Set to True to add checker CPUs
68        """
69        self.mem_mode = mem_mode
70        self.cpu_class = cpu_class
71        self.num_cpus = num_cpus
72        self.checker = checker
73
74    def create_cpus(self):
75        """Return a list of CPU objects to add to a system."""
76        cpus = [ self.cpu_class(cpu_id=i, clock='2GHz')
77                 for i in range(self.num_cpus) ]
78        if self.checker:
79            for c in cpus:
80                c.addCheckerCpu()
81        return cpus
82
83    def create_caches_private(self, cpu):
84        """Add private caches to a CPU.
85
86        Arguments:
87          cpu -- CPU instance to work on.
88        """
89        cpu.addPrivateSplitL1Caches(L1Cache(size='32kB', assoc=1),
90                                    L1Cache(size='32kB', assoc=4))
91
92    def create_caches_shared(self, system):
93        """Add shared caches to a system.
94
95        Arguments:
96          system -- System to work on.
97
98        Returns:
99          A bus that CPUs should use to connect to the shared cache.
100        """
101        system.toL2Bus = CoherentBus(clock='2GHz')
102        system.l2c = L2Cache(clock='2GHz', size='4MB', assoc=8)
103        system.l2c.cpu_side = system.toL2Bus.master
104        system.l2c.mem_side = system.membus.slave
105        return system.toL2Bus
106
107    def init_cpu(self, system, cpu, sha_bus):
108        """Initialize a CPU.
109
110        Arguments:
111          system -- System to work on.
112          cpu -- CPU to initialize.
113        """
114        if not cpu.switched_out:
115            self.create_caches_private(cpu)
116            cpu.createInterruptController()
117            cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
118                                system.membus)
119
120    def init_kvm(self, system):
121        """Do KVM-specific system initialization.
122
123        Arguments:
124          system -- System to work on.
125        """
126        system.vm = KvmVM()
127
128    def init_system(self, system):
129        """Initialize a system.
130
131        Arguments:
132          system -- System to initialize.
133        """
134        system.cpu = self.create_cpus()
135
136        if _have_kvm_support and \
137                any([isinstance(c, BaseKvmCPU) for c in system.cpu]):
138            self.init_kvm(system)
139
140        sha_bus = self.create_caches_shared(system)
141        for cpu in system.cpu:
142            self.init_cpu(system, cpu, sha_bus)
143
144    @abstractmethod
145    def create_system(self):
146        """Create an return an initialized system."""
147        pass
148
149    @abstractmethod
150    def create_root(self):
151        """Create and return a simulation root using the system
152        defined by this class."""
153        pass
154
155class BaseFSSystem(BaseSystem):
156    """Basic full system builder."""
157
158    def __init__(self, **kwargs):
159        BaseSystem.__init__(self, **kwargs)
160
161    def init_system(self, system):
162        BaseSystem.init_system(self, system)
163
164        #create the iocache
165        system.iocache = IOCache(clock='1GHz', addr_ranges=system.mem_ranges)
166        system.iocache.cpu_side = system.iobus.master
167        system.iocache.mem_side = system.membus.slave
168
169    def create_root(self):
170        system = self.create_system()
171        m5.ticks.setGlobalFrequency('1THz')
172        return Root(full_system=True, system=system)
173
174class BaseFSSystemUniprocessor(BaseFSSystem):
175    """Basic full system builder for uniprocessor systems.
176
177    Note: This class is only really needed to provide backwards
178    compatibility in existing test cases.
179    """
180
181    def __init__(self, **kwargs):
182        BaseFSSystem.__init__(self, **kwargs)
183
184    def create_caches_private(self, cpu):
185        cpu.addTwoLevelCacheHierarchy(L1Cache(size='32kB', assoc=1),
186                                      L1Cache(size='32kB', assoc=4),
187                                      L2Cache(size='4MB', assoc=8))
188
189    def create_caches_shared(self, system):
190        return None
191
192class BaseFSSwitcheroo(BaseFSSystem):
193    """Uniprocessor system prepared for CPU switching"""
194
195    def __init__(self, cpu_classes, **kwargs):
196        BaseFSSystem.__init__(self, **kwargs)
197        self.cpu_classes = tuple(cpu_classes)
198
199    def create_cpus(self):
200        cpus = [ cclass(cpu_id=0, clock='2GHz', switched_out=True)
201                 for cclass in self.cpu_classes ]
202        cpus[0].switched_out = False
203        return cpus
204