vexpress_gem5_v2_base.dtsi revision 14114:ed18eaf9d344
1/* 2 * Copyright (c) 2015-2017 ARM Limited 3 * All rights reserved 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Andreas Sandberg 29 */ 30 31/ { 32 arm,hbi = <0x0>; 33 arm,vexpress,site = <0xf>; 34 interrupt-parent = <&gic>; 35 #address-cells = <2>; 36 #size-cells = <2>; 37 38 gic: interrupt-controller@2c000000 { 39 compatible = "arm,gic-v3"; 40 #interrupt-cells = <0x3>; 41 #address-cells = <0x2>; 42 interrupt-controller; 43 redistributor-stride = <0x0 0x40000>; // 256kB stride 44 reg = <0x0 0x2c000000 0x0 0x10000 45 0x0 0x2c010000 0x0 0x2000000 // room for 128 redistributors using 128K each (256K strided...) 46 0x0 0x0 0x0 0x0>; 47 interrupts = <1 9 0xf04>; 48 #size-cells = <0x2>; 49 linux,phandle = <0x1>; 50 phandle = <0x1>; 51 }; 52 53 timer { 54 compatible = "arm,cortex-a15-timer", 55 "arm,armv7-timer"; 56 interrupts = <1 13 0xf08>, 57 <1 14 0xf08>, 58 <1 11 0xf08>, 59 <1 10 0xf08>; 60 clocks = <&osc_sys>; 61 clock-names="apb_pclk"; 62 }; 63 64 pci { 65 compatible = "pci-host-ecam-generic"; 66 device_type = "pci"; 67 #address-cells = <0x3>; 68 #size-cells = <0x2>; 69 #interrupt-cells = <0x1>; 70 71 reg = <0x0 0x30000000 0x0 0x10000000>; 72 73 ranges = <0x01000000 0x0 0x00000000 0x0 0x2f000000 0x0 0x00010000>, 74 <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>; 75 76 /* 77 child unit address, #cells = #address-cells 78 child interrupt specifier, #cells = #interrupt-cells (INTA = 1, INTB = 2, INTC = 3 and INTD = 4) 79 interrupt-parent, phandle 80 parent unit address, #cells = #address-cells@gic 81 parent interrupt specifier, #cells = #interrupt-cells@gic 82 */ 83 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x44 0x1 84 0x800 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x45 0x1 85 0x1000 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x46 0x1 86 0x1800 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x47 0x1>; 87 88 interrupt-map-mask = <0x001800 0x0 0x0 0x0>; 89 dma-coherent; 90 }; 91 92 kmi@1c060000 { 93 compatible = "arm,pl050", "arm,primecell"; 94 reg = <0x0 0x1c060000 0x0 0x1000>; 95 interrupts = <0 12 4>; 96 clocks = <&v2m_clk24mhz>, <&osc_smb>; 97 clock-names = "KMIREFCLK", "apb_pclk"; 98 }; 99 100 kmi@1c070000 { 101 compatible = "arm,pl050", "arm,primecell"; 102 reg = <0x0 0x1c070000 0x0 0x1000>; 103 interrupts = <0 13 4>; 104 clocks = <&v2m_clk24mhz>, <&osc_smb>; 105 clock-names = "KMIREFCLK", "apb_pclk"; 106 }; 107 108 uart0: uart@1c090000 { 109 compatible = "arm,pl011", "arm,primecell"; 110 reg = <0x0 0x1c090000 0x0 0x1000>; 111 interrupts = <0 5 4>; 112 clocks = <&osc_peripheral>, <&osc_smb>; 113 clock-names = "uartclk", "apb_pclk"; 114 }; 115 116 rtc@1c170000 { 117 compatible = "arm,pl031", "arm,primecell"; 118 reg = <0x0 0x1c170000 0x0 0x1000>; 119 interrupts = <0 4 4>; 120 clocks = <&osc_smb>; 121 clock-names = "apb_pclk"; 122 }; 123 124 v2m_clk24mhz: clk24mhz { 125 compatible = "fixed-clock"; 126 #clock-cells = <0>; 127 clock-frequency = <24000000>; 128 clock-output-names = "v2m:clk24mhz"; 129 }; 130 131 132 v2m_sysreg: sysreg@1c010000 { 133 compatible = "arm,vexpress-sysreg"; 134 reg = <0 0x1c010000 0x0 0x1000>; 135 gpio-controller; 136 #gpio-cells = <2>; 137 }; 138 139 vio@1c130000 { 140 compatible = "virtio,mmio"; 141 reg = <0 0x1c130000 0x0 0x1000>; 142 interrupts = <0 42 4>; 143 }; 144 145 vio@1c140000 { 146 compatible = "virtio,mmio"; 147 reg = <0 0x1c140000 0x0 0x1000>; 148 interrupts = <0 43 4>; 149 }; 150 151 dcc { 152 compatible = "arm,vexpress,config-bus"; 153 arm,vexpress,config-bridge = <&v2m_sysreg>; 154 155 osc_pxl: osc@5 { 156 compatible = "arm,vexpress-osc"; 157 arm,vexpress-sysreg,func = <1 5>; 158 freq-range = <23750000 1000000000>; 159 #clock-cells = <0>; 160 clock-output-names = "oscclk5"; 161 }; 162 163 osc_smb: osc@6 { 164 compatible = "arm,vexpress-osc"; 165 arm,vexpress-sysreg,func = <1 6>; 166 freq-range = <20000000 50000000>; 167 #clock-cells = <0>; 168 clock-output-names = "oscclk6"; 169 }; 170 171 osc_sys: osc@7 { 172 compatible = "arm,vexpress-osc"; 173 arm,vexpress-sysreg,func = <1 7>; 174 freq-range = <20000000 60000000>; 175 #clock-cells = <0>; 176 clock-output-names = "oscclk7"; 177 }; 178 }; 179 180 181 mcc { 182 compatible = "arm,vexpress,config-bus"; 183 arm,vexpress,config-bridge = <&v2m_sysreg>; 184 arm,vexpress,site = <0>; 185 186 osc_peripheral: osc@2 { 187 compatible = "arm,vexpress-osc"; 188 arm,vexpress-sysreg,func = <1 2>; 189 freq-range = <24000000 24000000>; 190 #clock-cells = <0>; 191 clock-output-names = "v2m:oscclk2"; 192 }; 193 }; 194}; 195