vexpress_gem5_v2_base.dtsi revision 14114
113510Sjairo.balart@metempsy.com/* 213510Sjairo.balart@metempsy.com * Copyright (c) 2015-2017 ARM Limited 313510Sjairo.balart@metempsy.com * All rights reserved 413510Sjairo.balart@metempsy.com * 513510Sjairo.balart@metempsy.com * Redistribution and use in source and binary forms, with or without 613510Sjairo.balart@metempsy.com * modification, are permitted provided that the following conditions are 713510Sjairo.balart@metempsy.com * met: redistributions of source code must retain the above copyright 813510Sjairo.balart@metempsy.com * notice, this list of conditions and the following disclaimer; 913510Sjairo.balart@metempsy.com * redistributions in binary form must reproduce the above copyright 1013510Sjairo.balart@metempsy.com * notice, this list of conditions and the following disclaimer in the 1113510Sjairo.balart@metempsy.com * documentation and/or other materials provided with the distribution; 1213510Sjairo.balart@metempsy.com * neither the name of the copyright holders nor the names of its 1313510Sjairo.balart@metempsy.com * contributors may be used to endorse or promote products derived from 1413510Sjairo.balart@metempsy.com * this software without specific prior written permission. 1513510Sjairo.balart@metempsy.com * 1613510Sjairo.balart@metempsy.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1713510Sjairo.balart@metempsy.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1813510Sjairo.balart@metempsy.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1913510Sjairo.balart@metempsy.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2013510Sjairo.balart@metempsy.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2113510Sjairo.balart@metempsy.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2213510Sjairo.balart@metempsy.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2313510Sjairo.balart@metempsy.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2413510Sjairo.balart@metempsy.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2513510Sjairo.balart@metempsy.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2613510Sjairo.balart@metempsy.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2713510Sjairo.balart@metempsy.com * 2813510Sjairo.balart@metempsy.com * Authors: Andreas Sandberg 2913510Sjairo.balart@metempsy.com */ 3013510Sjairo.balart@metempsy.com 3113510Sjairo.balart@metempsy.com/ { 3213510Sjairo.balart@metempsy.com arm,hbi = <0x0>; 3313510Sjairo.balart@metempsy.com arm,vexpress,site = <0xf>; 3413510Sjairo.balart@metempsy.com interrupt-parent = <&gic>; 3513510Sjairo.balart@metempsy.com #address-cells = <2>; 3613510Sjairo.balart@metempsy.com #size-cells = <2>; 3713510Sjairo.balart@metempsy.com 3813510Sjairo.balart@metempsy.com gic: interrupt-controller@2c000000 { 3913510Sjairo.balart@metempsy.com compatible = "arm,gic-v3"; 4013510Sjairo.balart@metempsy.com #interrupt-cells = <0x3>; 4113510Sjairo.balart@metempsy.com #address-cells = <0x2>; 4213510Sjairo.balart@metempsy.com interrupt-controller; 4313879Sgiacomo.travaglini@arm.com redistributor-stride = <0x0 0x40000>; // 256kB stride 4413510Sjairo.balart@metempsy.com reg = <0x0 0x2c000000 0x0 0x10000 4513879Sgiacomo.travaglini@arm.com 0x0 0x2c010000 0x0 0x2000000 // room for 128 redistributors using 128K each (256K strided...) 4613510Sjairo.balart@metempsy.com 0x0 0x0 0x0 0x0>; 4713510Sjairo.balart@metempsy.com interrupts = <1 9 0xf04>; 4813510Sjairo.balart@metempsy.com #size-cells = <0x2>; 4913510Sjairo.balart@metempsy.com linux,phandle = <0x1>; 5013510Sjairo.balart@metempsy.com phandle = <0x1>; 5113510Sjairo.balart@metempsy.com }; 5213510Sjairo.balart@metempsy.com 5313510Sjairo.balart@metempsy.com timer { 5413510Sjairo.balart@metempsy.com compatible = "arm,cortex-a15-timer", 5513510Sjairo.balart@metempsy.com "arm,armv7-timer"; 5613510Sjairo.balart@metempsy.com interrupts = <1 13 0xf08>, 5713510Sjairo.balart@metempsy.com <1 14 0xf08>, 5814114Schunchenhsu@google.com <1 11 0xf08>, 5914114Schunchenhsu@google.com <1 10 0xf08>; 6013510Sjairo.balart@metempsy.com clocks = <&osc_sys>; 6113510Sjairo.balart@metempsy.com clock-names="apb_pclk"; 6213510Sjairo.balart@metempsy.com }; 6313510Sjairo.balart@metempsy.com 6413510Sjairo.balart@metempsy.com pci { 6513510Sjairo.balart@metempsy.com compatible = "pci-host-ecam-generic"; 6613510Sjairo.balart@metempsy.com device_type = "pci"; 6713510Sjairo.balart@metempsy.com #address-cells = <0x3>; 6813510Sjairo.balart@metempsy.com #size-cells = <0x2>; 6913510Sjairo.balart@metempsy.com #interrupt-cells = <0x1>; 7013510Sjairo.balart@metempsy.com 7113510Sjairo.balart@metempsy.com reg = <0x0 0x30000000 0x0 0x10000000>; 7213510Sjairo.balart@metempsy.com 7313510Sjairo.balart@metempsy.com ranges = <0x01000000 0x0 0x00000000 0x0 0x2f000000 0x0 0x00010000>, 7413510Sjairo.balart@metempsy.com <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>; 7513510Sjairo.balart@metempsy.com 7613510Sjairo.balart@metempsy.com /* 7713510Sjairo.balart@metempsy.com child unit address, #cells = #address-cells 7813510Sjairo.balart@metempsy.com child interrupt specifier, #cells = #interrupt-cells (INTA = 1, INTB = 2, INTC = 3 and INTD = 4) 7913510Sjairo.balart@metempsy.com interrupt-parent, phandle 8013510Sjairo.balart@metempsy.com parent unit address, #cells = #address-cells@gic 8113510Sjairo.balart@metempsy.com parent interrupt specifier, #cells = #interrupt-cells@gic 8213510Sjairo.balart@metempsy.com */ 8313510Sjairo.balart@metempsy.com interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x44 0x1 8413510Sjairo.balart@metempsy.com 0x800 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x45 0x1 8513510Sjairo.balart@metempsy.com 0x1000 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x46 0x1 8613510Sjairo.balart@metempsy.com 0x1800 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x47 0x1>; 8713510Sjairo.balart@metempsy.com 8813510Sjairo.balart@metempsy.com interrupt-map-mask = <0x001800 0x0 0x0 0x0>; 8913510Sjairo.balart@metempsy.com dma-coherent; 9013510Sjairo.balart@metempsy.com }; 9113510Sjairo.balart@metempsy.com 9213510Sjairo.balart@metempsy.com kmi@1c060000 { 9313510Sjairo.balart@metempsy.com compatible = "arm,pl050", "arm,primecell"; 9413510Sjairo.balart@metempsy.com reg = <0x0 0x1c060000 0x0 0x1000>; 9513510Sjairo.balart@metempsy.com interrupts = <0 12 4>; 9613510Sjairo.balart@metempsy.com clocks = <&v2m_clk24mhz>, <&osc_smb>; 9713510Sjairo.balart@metempsy.com clock-names = "KMIREFCLK", "apb_pclk"; 9813510Sjairo.balart@metempsy.com }; 9913510Sjairo.balart@metempsy.com 10013510Sjairo.balart@metempsy.com kmi@1c070000 { 10113510Sjairo.balart@metempsy.com compatible = "arm,pl050", "arm,primecell"; 10213510Sjairo.balart@metempsy.com reg = <0x0 0x1c070000 0x0 0x1000>; 10313510Sjairo.balart@metempsy.com interrupts = <0 13 4>; 10413510Sjairo.balart@metempsy.com clocks = <&v2m_clk24mhz>, <&osc_smb>; 10513510Sjairo.balart@metempsy.com clock-names = "KMIREFCLK", "apb_pclk"; 10613510Sjairo.balart@metempsy.com }; 10713510Sjairo.balart@metempsy.com 10813510Sjairo.balart@metempsy.com uart0: uart@1c090000 { 10913510Sjairo.balart@metempsy.com compatible = "arm,pl011", "arm,primecell"; 11013510Sjairo.balart@metempsy.com reg = <0x0 0x1c090000 0x0 0x1000>; 11113510Sjairo.balart@metempsy.com interrupts = <0 5 4>; 11213510Sjairo.balart@metempsy.com clocks = <&osc_peripheral>, <&osc_smb>; 11313510Sjairo.balart@metempsy.com clock-names = "uartclk", "apb_pclk"; 11413510Sjairo.balart@metempsy.com }; 11513510Sjairo.balart@metempsy.com 11613510Sjairo.balart@metempsy.com rtc@1c170000 { 11713510Sjairo.balart@metempsy.com compatible = "arm,pl031", "arm,primecell"; 11813510Sjairo.balart@metempsy.com reg = <0x0 0x1c170000 0x0 0x1000>; 11913510Sjairo.balart@metempsy.com interrupts = <0 4 4>; 12013510Sjairo.balart@metempsy.com clocks = <&osc_smb>; 12113510Sjairo.balart@metempsy.com clock-names = "apb_pclk"; 12213510Sjairo.balart@metempsy.com }; 12313510Sjairo.balart@metempsy.com 12413510Sjairo.balart@metempsy.com v2m_clk24mhz: clk24mhz { 12513510Sjairo.balart@metempsy.com compatible = "fixed-clock"; 12613510Sjairo.balart@metempsy.com #clock-cells = <0>; 12713510Sjairo.balart@metempsy.com clock-frequency = <24000000>; 12813510Sjairo.balart@metempsy.com clock-output-names = "v2m:clk24mhz"; 12913510Sjairo.balart@metempsy.com }; 13013510Sjairo.balart@metempsy.com 13113510Sjairo.balart@metempsy.com 13213510Sjairo.balart@metempsy.com v2m_sysreg: sysreg@1c010000 { 13313510Sjairo.balart@metempsy.com compatible = "arm,vexpress-sysreg"; 13413510Sjairo.balart@metempsy.com reg = <0 0x1c010000 0x0 0x1000>; 13513510Sjairo.balart@metempsy.com gpio-controller; 13613510Sjairo.balart@metempsy.com #gpio-cells = <2>; 13713510Sjairo.balart@metempsy.com }; 13813510Sjairo.balart@metempsy.com 13913510Sjairo.balart@metempsy.com vio@1c130000 { 14013510Sjairo.balart@metempsy.com compatible = "virtio,mmio"; 14113510Sjairo.balart@metempsy.com reg = <0 0x1c130000 0x0 0x1000>; 14213510Sjairo.balart@metempsy.com interrupts = <0 42 4>; 14313510Sjairo.balart@metempsy.com }; 14413510Sjairo.balart@metempsy.com 14513510Sjairo.balart@metempsy.com vio@1c140000 { 14613510Sjairo.balart@metempsy.com compatible = "virtio,mmio"; 14713510Sjairo.balart@metempsy.com reg = <0 0x1c140000 0x0 0x1000>; 14813510Sjairo.balart@metempsy.com interrupts = <0 43 4>; 14913510Sjairo.balart@metempsy.com }; 15013510Sjairo.balart@metempsy.com 15113510Sjairo.balart@metempsy.com dcc { 15213510Sjairo.balart@metempsy.com compatible = "arm,vexpress,config-bus"; 15313510Sjairo.balart@metempsy.com arm,vexpress,config-bridge = <&v2m_sysreg>; 15413510Sjairo.balart@metempsy.com 15513510Sjairo.balart@metempsy.com osc_pxl: osc@5 { 15613510Sjairo.balart@metempsy.com compatible = "arm,vexpress-osc"; 15713510Sjairo.balart@metempsy.com arm,vexpress-sysreg,func = <1 5>; 15813510Sjairo.balart@metempsy.com freq-range = <23750000 1000000000>; 15913510Sjairo.balart@metempsy.com #clock-cells = <0>; 16013510Sjairo.balart@metempsy.com clock-output-names = "oscclk5"; 16113510Sjairo.balart@metempsy.com }; 16213510Sjairo.balart@metempsy.com 16313510Sjairo.balart@metempsy.com osc_smb: osc@6 { 16413510Sjairo.balart@metempsy.com compatible = "arm,vexpress-osc"; 16513510Sjairo.balart@metempsy.com arm,vexpress-sysreg,func = <1 6>; 16613510Sjairo.balart@metempsy.com freq-range = <20000000 50000000>; 16713510Sjairo.balart@metempsy.com #clock-cells = <0>; 16813510Sjairo.balart@metempsy.com clock-output-names = "oscclk6"; 16913510Sjairo.balart@metempsy.com }; 17013510Sjairo.balart@metempsy.com 17113510Sjairo.balart@metempsy.com osc_sys: osc@7 { 17213510Sjairo.balart@metempsy.com compatible = "arm,vexpress-osc"; 17313510Sjairo.balart@metempsy.com arm,vexpress-sysreg,func = <1 7>; 17413510Sjairo.balart@metempsy.com freq-range = <20000000 60000000>; 17513510Sjairo.balart@metempsy.com #clock-cells = <0>; 17613510Sjairo.balart@metempsy.com clock-output-names = "oscclk7"; 17713510Sjairo.balart@metempsy.com }; 17813510Sjairo.balart@metempsy.com }; 17913510Sjairo.balart@metempsy.com 18013510Sjairo.balart@metempsy.com 18113510Sjairo.balart@metempsy.com mcc { 18213510Sjairo.balart@metempsy.com compatible = "arm,vexpress,config-bus"; 18313510Sjairo.balart@metempsy.com arm,vexpress,config-bridge = <&v2m_sysreg>; 18413510Sjairo.balart@metempsy.com arm,vexpress,site = <0>; 18513510Sjairo.balart@metempsy.com 18613510Sjairo.balart@metempsy.com osc_peripheral: osc@2 { 18713510Sjairo.balart@metempsy.com compatible = "arm,vexpress-osc"; 18813510Sjairo.balart@metempsy.com arm,vexpress-sysreg,func = <1 2>; 18913510Sjairo.balart@metempsy.com freq-range = <24000000 24000000>; 19013510Sjairo.balart@metempsy.com #clock-cells = <0>; 19113510Sjairo.balart@metempsy.com clock-output-names = "v2m:oscclk2"; 19213510Sjairo.balart@metempsy.com }; 19313510Sjairo.balart@metempsy.com }; 19413510Sjairo.balart@metempsy.com}; 195