vexpress_gem5_v1.dtsi revision 11348
111348Sandreas.sandberg@arm.com/* 211348Sandreas.sandberg@arm.com * Copyright (c) 2015-2016 ARM Limited 311348Sandreas.sandberg@arm.com * All rights reserved 411348Sandreas.sandberg@arm.com * 511348Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 611348Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 711348Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright 811348Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer; 911348Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright 1011348Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 1111348Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution; 1211348Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 1311348Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 1411348Sandreas.sandberg@arm.com * this software without specific prior written permission. 1511348Sandreas.sandberg@arm.com * 1611348Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711348Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811348Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911348Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011348Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111348Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211348Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311348Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411348Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511348Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611348Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711348Sandreas.sandberg@arm.com * 2811348Sandreas.sandberg@arm.com * Authors: Andreas Sandberg 2911348Sandreas.sandberg@arm.com */ 3011348Sandreas.sandberg@arm.com 3111348Sandreas.sandberg@arm.com/ { 3211348Sandreas.sandberg@arm.com arm,hbi = <0x0>; 3311348Sandreas.sandberg@arm.com arm,vexpress,site = <0xf>; 3411348Sandreas.sandberg@arm.com interrupt-parent = <&gic>; 3511348Sandreas.sandberg@arm.com #address-cells = <2>; 3611348Sandreas.sandberg@arm.com #size-cells = <2>; 3711348Sandreas.sandberg@arm.com 3811348Sandreas.sandberg@arm.com gic: interrupt-controller@2c001000 { 3911348Sandreas.sandberg@arm.com compatible = "gem5,gic", "arm,gic-400"; 4011348Sandreas.sandberg@arm.com #interrupt-cells = <3>; 4111348Sandreas.sandberg@arm.com #address-cells = <0>; 4211348Sandreas.sandberg@arm.com interrupt-controller; 4311348Sandreas.sandberg@arm.com reg = <0 0x2c001000 0 0x1000>, 4411348Sandreas.sandberg@arm.com <0 0x2c002000 0 0x1000>, 4511348Sandreas.sandberg@arm.com <0 0x2c004000 0 0x2000>, 4611348Sandreas.sandberg@arm.com <0 0x2c006000 0 0x2000>; 4711348Sandreas.sandberg@arm.com interrupts = <1 9 0xf04>; 4811348Sandreas.sandberg@arm.com }; 4911348Sandreas.sandberg@arm.com 5011348Sandreas.sandberg@arm.com 5111348Sandreas.sandberg@arm.com timer { 5211348Sandreas.sandberg@arm.com compatible = "arm,cortex-a15-timer", 5311348Sandreas.sandberg@arm.com "arm,armv7-timer"; 5411348Sandreas.sandberg@arm.com interrupts = <1 13 0xff01>, 5511348Sandreas.sandberg@arm.com <1 14 0xff01>, 5611348Sandreas.sandberg@arm.com <1 11 0xff01>; 5711348Sandreas.sandberg@arm.com clocks = <&osc_sys>; 5811348Sandreas.sandberg@arm.com clock-names="apb_pclk"; 5911348Sandreas.sandberg@arm.com }; 6011348Sandreas.sandberg@arm.com 6111348Sandreas.sandberg@arm.com pci { 6211348Sandreas.sandberg@arm.com compatible = "pci-host-ecam-generic"; 6311348Sandreas.sandberg@arm.com device_type = "pci"; 6411348Sandreas.sandberg@arm.com #address-cells = <0x3>; 6511348Sandreas.sandberg@arm.com #size-cells = <0x2>; 6611348Sandreas.sandberg@arm.com #interrupt-cells = <0x1>; 6711348Sandreas.sandberg@arm.com 6811348Sandreas.sandberg@arm.com reg = <0x0 0x30000000 0x0 0x10000000>; 6911348Sandreas.sandberg@arm.com 7011348Sandreas.sandberg@arm.com ranges = <0x01000000 0x0 0x00000000 0x0 0x2f000000 0x0 0x00010000>, 7111348Sandreas.sandberg@arm.com <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>; 7211348Sandreas.sandberg@arm.com 7311348Sandreas.sandberg@arm.com interrupt-map = <0x000000 0x0 0x0 0 &gic 0 68 1>, 7411348Sandreas.sandberg@arm.com <0x000800 0x0 0x0 0 &gic 0 69 1>, 7511348Sandreas.sandberg@arm.com <0x001000 0x0 0x0 0 &gic 0 70 1>, 7611348Sandreas.sandberg@arm.com <0x001800 0x0 0x0 0 &gic 0 71 1>; 7711348Sandreas.sandberg@arm.com 7811348Sandreas.sandberg@arm.com interrupt-map-mask = <0x001800 0x0 0x0 0x0>; 7911348Sandreas.sandberg@arm.com dma-coherent; 8011348Sandreas.sandberg@arm.com }; 8111348Sandreas.sandberg@arm.com 8211348Sandreas.sandberg@arm.com /* Ths HDLCD controller driver hasn't reached mainline 8311348Sandreas.sandberg@arm.com * yet. Disable it by default in the platform until the DT 8411348Sandreas.sandberg@arm.com * bindings have stabilize. 8511348Sandreas.sandberg@arm.com */ 8611348Sandreas.sandberg@arm.com hdlcd0: hdlcd@2b000000 { 8711348Sandreas.sandberg@arm.com compatible = "arm,hdlcd"; 8811348Sandreas.sandberg@arm.com reg = <0x0 0x2b000000 0x0 0x1000>; 8911348Sandreas.sandberg@arm.com interrupts = <0 63 4>; 9011348Sandreas.sandberg@arm.com clocks = <&osc_pxl>; 9111348Sandreas.sandberg@arm.com clock-names = "pxlclk"; 9211348Sandreas.sandberg@arm.com 9311348Sandreas.sandberg@arm.com status = "disabled"; 9411348Sandreas.sandberg@arm.com }; 9511348Sandreas.sandberg@arm.com 9611348Sandreas.sandberg@arm.com kmi@1c060000 { 9711348Sandreas.sandberg@arm.com compatible = "arm,pl050", "arm,primecell"; 9811348Sandreas.sandberg@arm.com reg = <0x0 0x1c060000 0x0 0x1000>; 9911348Sandreas.sandberg@arm.com interrupts = <0 12 4>; 10011348Sandreas.sandberg@arm.com clocks = <&v2m_clk24mhz>, <&osc_smb>; 10111348Sandreas.sandberg@arm.com clock-names = "KMIREFCLK", "apb_pclk"; 10211348Sandreas.sandberg@arm.com }; 10311348Sandreas.sandberg@arm.com 10411348Sandreas.sandberg@arm.com kmi@1c070000 { 10511348Sandreas.sandberg@arm.com compatible = "arm,pl050", "arm,primecell"; 10611348Sandreas.sandberg@arm.com reg = <0x0 0x1c070000 0x0 0x1000>; 10711348Sandreas.sandberg@arm.com interrupts = <0 13 4>; 10811348Sandreas.sandberg@arm.com clocks = <&v2m_clk24mhz>, <&osc_smb>; 10911348Sandreas.sandberg@arm.com clock-names = "KMIREFCLK", "apb_pclk"; 11011348Sandreas.sandberg@arm.com }; 11111348Sandreas.sandberg@arm.com 11211348Sandreas.sandberg@arm.com uart0: uart@1c090000 { 11311348Sandreas.sandberg@arm.com compatible = "arm,pl011", "arm,primecell"; 11411348Sandreas.sandberg@arm.com reg = <0x0 0x1c090000 0x0 0x1000>; 11511348Sandreas.sandberg@arm.com interrupts = <0 5 4>; 11611348Sandreas.sandberg@arm.com clocks = <&osc_peripheral>, <&osc_smb>; 11711348Sandreas.sandberg@arm.com clock-names = "uartclk", "apb_pclk"; 11811348Sandreas.sandberg@arm.com }; 11911348Sandreas.sandberg@arm.com 12011348Sandreas.sandberg@arm.com rtc@1c170000 { 12111348Sandreas.sandberg@arm.com compatible = "arm,pl031", "arm,primecell"; 12211348Sandreas.sandberg@arm.com reg = <0x0 0x1c170000 0x0 0x1000>; 12311348Sandreas.sandberg@arm.com interrupts = <0 4 4>; 12411348Sandreas.sandberg@arm.com clocks = <&osc_smb>; 12511348Sandreas.sandberg@arm.com clock-names = "apb_pclk"; 12611348Sandreas.sandberg@arm.com }; 12711348Sandreas.sandberg@arm.com 12811348Sandreas.sandberg@arm.com v2m_clk24mhz: clk24mhz { 12911348Sandreas.sandberg@arm.com compatible = "fixed-clock"; 13011348Sandreas.sandberg@arm.com #clock-cells = <0>; 13111348Sandreas.sandberg@arm.com clock-frequency = <24000000>; 13211348Sandreas.sandberg@arm.com clock-output-names = "v2m:clk24mhz"; 13311348Sandreas.sandberg@arm.com }; 13411348Sandreas.sandberg@arm.com 13511348Sandreas.sandberg@arm.com 13611348Sandreas.sandberg@arm.com v2m_sysreg: sysreg@1c010000 { 13711348Sandreas.sandberg@arm.com compatible = "arm,vexpress-sysreg"; 13811348Sandreas.sandberg@arm.com reg = <0 0x1c010000 0x0 0x1000>; 13911348Sandreas.sandberg@arm.com gpio-controller; 14011348Sandreas.sandberg@arm.com #gpio-cells = <2>; 14111348Sandreas.sandberg@arm.com }; 14211348Sandreas.sandberg@arm.com 14311348Sandreas.sandberg@arm.com dcc { 14411348Sandreas.sandberg@arm.com compatible = "arm,vexpress,config-bus"; 14511348Sandreas.sandberg@arm.com arm,vexpress,config-bridge = <&v2m_sysreg>; 14611348Sandreas.sandberg@arm.com 14711348Sandreas.sandberg@arm.com osc_pxl: osc@5 { 14811348Sandreas.sandberg@arm.com compatible = "arm,vexpress-osc"; 14911348Sandreas.sandberg@arm.com arm,vexpress-sysreg,func = <1 5>; 15011348Sandreas.sandberg@arm.com freq-range = <23750000 1000000000>; 15111348Sandreas.sandberg@arm.com #clock-cells = <0>; 15211348Sandreas.sandberg@arm.com clock-output-names = "oscclk5"; 15311348Sandreas.sandberg@arm.com }; 15411348Sandreas.sandberg@arm.com 15511348Sandreas.sandberg@arm.com osc_smb: osc@6 { 15611348Sandreas.sandberg@arm.com compatible = "arm,vexpress-osc"; 15711348Sandreas.sandberg@arm.com arm,vexpress-sysreg,func = <1 6>; 15811348Sandreas.sandberg@arm.com freq-range = <20000000 50000000>; 15911348Sandreas.sandberg@arm.com #clock-cells = <0>; 16011348Sandreas.sandberg@arm.com clock-output-names = "oscclk6"; 16111348Sandreas.sandberg@arm.com }; 16211348Sandreas.sandberg@arm.com 16311348Sandreas.sandberg@arm.com osc_sys: osc@7 { 16411348Sandreas.sandberg@arm.com compatible = "arm,vexpress-osc"; 16511348Sandreas.sandberg@arm.com arm,vexpress-sysreg,func = <1 7>; 16611348Sandreas.sandberg@arm.com freq-range = <20000000 60000000>; 16711348Sandreas.sandberg@arm.com #clock-cells = <0>; 16811348Sandreas.sandberg@arm.com clock-output-names = "oscclk7"; 16911348Sandreas.sandberg@arm.com }; 17011348Sandreas.sandberg@arm.com }; 17111348Sandreas.sandberg@arm.com 17211348Sandreas.sandberg@arm.com 17311348Sandreas.sandberg@arm.com mcc { 17411348Sandreas.sandberg@arm.com compatible = "arm,vexpress,config-bus"; 17511348Sandreas.sandberg@arm.com arm,vexpress,config-bridge = <&v2m_sysreg>; 17611348Sandreas.sandberg@arm.com arm,vexpress,site = <0>; 17711348Sandreas.sandberg@arm.com 17811348Sandreas.sandberg@arm.com osc_peripheral: osc@2 { 17911348Sandreas.sandberg@arm.com compatible = "arm,vexpress-osc"; 18011348Sandreas.sandberg@arm.com arm,vexpress-sysreg,func = <1 2>; 18111348Sandreas.sandberg@arm.com freq-range = <24000000 24000000>; 18211348Sandreas.sandberg@arm.com #clock-cells = <0>; 18311348Sandreas.sandberg@arm.com clock-output-names = "v2m:oscclk2"; 18411348Sandreas.sandberg@arm.com }; 18511348Sandreas.sandberg@arm.com }; 18611348Sandreas.sandberg@arm.com}; 187