armv7.dts revision 11470
1/* 2 * Copyright (c) 2015-2016 ARM Limited 3 * All rights reserved 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Andreas Sandberg 29 */ 30 31/dts-v1/; 32 33#include CONF_PLATFORM 34 35#define CPU(n) \ 36 cpu@ ## n { \ 37 device_type = "cpu"; \ 38 compatible = "gem5,arm", "arm,cortex-a15"; \ 39 reg = < n >; \ 40 }; 41 42/ { 43 model = "V2P-CA15"; 44 compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress"; 45 46 memory@80000000 { 47 device_type = "memory"; 48 reg = <0 0x80000000 0x4 0x00000000>; 49 }; 50 51 cpus { 52 #address-cells = <1>; 53 #size-cells = <0>; 54 55 #if CONF_CPUS > 0 56 CPU(0) 57 #endif 58 #if CONF_CPUS > 1 59 CPU(1) 60 #endif 61 #if CONF_CPUS > 2 62 CPU(2) 63 #endif 64 #if CONF_CPUS > 3 65 CPU(3) 66 #endif 67 #if CONF_CPUS > 4 68 CPU(4) 69 #endif 70 #if CONF_CPUS > 5 71 CPU(5) 72 #endif 73 #if CONF_CPUS > 6 74 CPU(6) 75 #endif 76 #if CONF_CPUS > 7 77 CPU(7) 78 #endif 79 #if CONF_CPUS > 8 80 CPU(8) 81 #endif 82 #if CONF_CPUS > 9 83 CPU(9) 84 #endif 85 #if CONF_CPUS > 10 86 CPU(10) 87 #endif 88 #if CONF_CPUS > 11 89 CPU(11) 90 #endif 91 #if CONF_CPUS > 12 92 CPU(12) 93 #endif 94 #if CONF_CPUS > 13 95 CPU(13) 96 #endif 97 #if CONF_CPUS > 14 98 CPU(14) 99 #endif 100 #if CONF_CPUS > 15 101 CPU(15) 102 #endif 103 #if CONF_CPUS > 16 104 #error Unsupported number of CPUs 105 #endif 106 }; 107 108 virt-encoder { 109 compatible = "drm,virtual-encoder"; 110 port { 111 hdlcd0_virt_input: endpoint@0 { 112 remote-endpoint = <&hdlcd0_output>; 113 }; 114 }; 115 116 display-timings { 117 native-mode = <&timing0>; 118 119 timing0: timing_1080p60 { 120 /* 1920x1080-60 */ 121 clock-frequency = <148500000>; 122 hactive = <1920>; 123 vactive = <1080>; 124 hfront-porch = <148>; 125 hback-porch = <88>; 126 hsync-len = <44>; 127 vfront-porch = <36>; 128 vback-porch = <4>; 129 vsync-len = <5>; 130 }; 131 }; 132 }; 133}; 134 135&hdlcd0 { 136 status = "ok"; 137 138 port { 139 hdlcd0_output: endpoint@0 { 140 remote-endpoint = <&hdlcd0_virt_input>; 141 }; 142 }; 143}; 144