rpb.h revision 8013
1/*
2 * Copyright 1990 Hewlett-Packard Development Company, L.P.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25/*
26 * Defines for the architected startup addresses.
27 */
28#define HWRPB_ADDR	0x10000000	/* 256 MB */
29#define BOOT_ADDR	0x20000000	/* 512 MB */
30#define PGTBL_ADDR	0x40000000	/*   1 GB */
31
32/*
33 * Values for the "haltcode" field in the per-cpu portion of the HWRPB
34 *
35 * Bit defines for the "sysvar" field in the HWRPB.
36 * Each platform has different values for SYSBOARD and IOBOARD bits.
37 */
38#define HALT_PWRUP	0		/* power up */
39#define HALT_OPR	1		/* operator issued halt cmd */
40#define HALT_KSTK	2		/* kernel stack not valid */
41#define HALT_SCBB	3		/* invalid SCBB */
42#define HALT_PTBR	4		/* invalid PTBR */
43#define HALT_EXE	5		/* kernel executed halt instruction */
44#define HALT_DBLE	6		/* double error abort */
45
46/*
47 * Bit defines for the "state" field in the per-cpu portion of the HWRPB
48 */
49#define STATE_BIP	0x00000001	/* bootstrap in progress */
50#define STATE_RC	0x00000002	/* restart capable */
51#define STATE_PA	0x00000004	/* processor available to OS */
52#define STATE_PP	0x00000008	/* processor present */
53#define STATE_OH	0x00000010	/* operator halted */
54#define STATE_CV	0x00000020	/* context valid */
55#define STATE_PV	0x00000040	/* PALcode valid */
56#define STATE_PMV	0x00000080	/* PALcode memory valid */
57#define STATE_PL	0x00000100	/* PALcode loaded */
58#define STATE_HALT_MASK	0x00ff0000	/* Mask for Halt Requested field */
59#define STATE_DEFAULT	0x00000000	/* Default (no specific action) */
60#define STATE_SVRS_TERM	0x00010000	/* SAVE_TERM/RESTORE_TERM Exit */
61#define STATE_COLD_BOOT	0x00020000	/* Cold Bootstrap Requested */
62#define STATE_WARM_BOOT	0x00030000	/* Warm Bootstrap Requested */
63#define STATE_HALT	0x00040000	/* Remain halted (no restart) */
64
65
66#define SV_PF_RSVD	0x00000000	/* RESERVED */
67#define SV_RESERVED	0x00000000	/* All STS bits; 0 for back compat */
68#define SV_MPCAP	0x00000001	/* MP capable */
69#define SV_PF_UNITED	0x00000020	/* United */
70#define SV_PF_SEPARATE	0x00000040	/* Separate */
71#define SV_PF_FULLBB	0x00000060	/* Full battery backup */
72#define SV_POWERFAIL	0x000000e0	/* Powerfail implementation */
73#define SV_PF_RESTART	0x00000100	/* Powerfail restart */
74
75#define SV_GRAPHICS	0x00000200	/* Embedded graphics processor */
76
77#define SV_STS_MASK	0x0000fc00	/* STS bits - system and I/O board */
78#define SV_SANDPIPER	0x00000400	/* others define system platforms */
79#define SV_FLAMINGO	0x00000800	/* STS BIT SETTINGS */
80#define SV_HOTPINK	0x00000c00	/* STS BIT SETTINGS */
81#define SV_FLAMINGOPLUS	0x00001000	/* STS BIT SETTINGS */
82#define SV_ULTRA	0x00001400	/* STS BIT SETTINGS */
83#define SV_SANDPLUS	0x00001800	/* STS BIT SETTINGS */
84#define SV_SANDPIPER45	0x00001c00	/* STS BIT SETTINGS */
85#define SV_FLAMINGO45	0x00002000	/* STS BIT SETTINGS */
86
87#define SV_SABLE	0x00000400	/* STS BIT SETTINGS */
88
89#define SV_KN20AA	0x00000400	/* STS BIT SETTINGS */
90
91/*
92 * Values for the "console type" field in the CTB portion of the HWRPB
93 */
94#define CONS_NONE	0		/* no console present */
95#define CONS_SRVC	1		/* console is service processor */
96#define CONS_DZ		2		/* console is dz/dl VT device */
97#define CONS_GRPH	3		/* cons is gfx dev w/ dz/dl keybd*/
98#define CONS_REM	4		/* cons is remote, protocal enet/MOP */
99
100/*
101 * PALcode variants that we're interested in.
102 * Used as indices into the "palrev_avail" array in the per-cpu portion
103 * of the HWRPB.
104 */
105#define PALvar_reserved	0
106#define PALvar_OpenVMS	1
107#define PALvar_OSF1	2
108
109/*
110 * The Alpha restart parameter block, which is a page or 2 in low memory
111 */
112struct rpb {
113    struct rpb *rpb_selfref;	/* 000: physical self-reference */
114    long  rpb_string;		/* 008: contains string "HWRPB" */
115    long  rpb_vers;		/* 010: HWRPB version number */
116    ulong rpb_size;		/* 018: bytes in RPB perCPU CTB CRB MEMDSC */
117    ulong rpb_cpuid;		/* 020: primary cpu id */
118    ulong rpb_pagesize;		/* 028: page size in bytes */
119    ulong rpb_addrbits;		/* 030: number of phys addr bits */
120    ulong rpb_maxasn;		/* 038: max valid ASN */
121    char  rpb_ssn[16];		/* 040: system serial num: 10 ascii chars */
122    ulong grpb_systype;		/* 050: system type */
123    long  rpb_sysvar;		/* 058: system variation */
124    long  rpb_sysrev;		/* 060: system revision */
125    ulong rpb_clock;		/* 068: scaled interval clock intr freq */
126    ulong rpb_counter;		/* 070: cycle counter frequency */
127    ulong rpb_vptb;		/* 078: virtual page table base */
128    long  rpb_res1;		/* 080: reserved */
129    ulong rpb_trans_off;	/* 088: offset to translation buffer hint */
130    ulong rpb_numprocs;		/* 090: number of processor slots */
131    ulong rpb_slotsize;		/* 098: per-cpu slot size */
132    ulong rpb_percpu_off;	/* 0A0: offset to per_cpu slots */
133    ulong rpb_num_ctb;		/* 0A8: number of CTBs */
134    ulong rpb_ctb_size;		/* 0B0: bytes in largest CTB */
135    ulong rpb_ctb_off;		/* 0B8: offset to CTB (cons term block) */
136    ulong rpb_crb_off;		/* 0C0: offset to CRB (cons routine block) */
137    ulong rpb_mdt_off;		/* 0C8: offset to memory descriptor table */
138    ulong rpb_config_off;	/* 0D0: offset to config data block */
139    ulong rpb_fru_off;		/* 0D8: offset to FRU table */
140    void  (*rpb_saveterm)();	/* 0E0: virt addr of save term routine */
141    long  rpb_saveterm_pv;	/* 0E8: proc value for save term routine */
142    void  (*rpb_rstrterm)();	/* 0F0: virt addr of restore term routine */
143    long  rpb_rstrterm_pv;	/* 0F8: proc value for restore term routine */
144    void  (*rpb_restart)();	/* 100: virt addr of CPU restart routine */
145    long  rpb_restart_pv;	/* 108: proc value for CPU restart routine */
146    long  rpb_software;		/* 110: used to determine presence of kdebug */
147    long  rpb_hardware;		/* 118: reserved for hardware */
148    long  rpb_checksum;		/* 120: checksum of prior entries in rpb */
149    long  rpb_rxrdy;		/* 128: receive ready bitmask */
150    long  rpb_txrdy;		/* 130: transmit ready bitmask */
151    ulong rpb_dsr_off;		/* 138: Dynamic System Recog. offset */
152};
153
154#define rpb_kdebug rpb_software
155
156#define OSF_HWRPB_ADDR	((vm_offset_t)(-1L << 23))
157
158/*
159 * This is the format for the boot/restart HWPCB.  It must match the
160 * initial fields of the pcb structure as defined in pcb.h, but must
161 * additionally contain the appropriate amount of padding to line up
162 * with formats used by other palcode types.
163 */
164struct bootpcb {
165    long rpb_ksp;		/* 000: kernel stack pointer */
166    long rpb_usp;		/* 008: user stack pointer */
167    long rpb_ptbr;		/* 010: page table base register */
168    int  rpb_cc;		/* 018: cycle counter */
169    int  rpb_asn;		/* 01C: address space number */
170    long rpb_proc_uniq;		/* 020: proc/thread unique value */
171    long rpb_fen;		/* 028: floating point enable */
172    long rpb_palscr[2];		/* 030: pal scratch area */
173    long rpb_pcbpad[8];		/* 040: padding for fixed size */
174};
175
176/*
177 * Inter-Console Communications Buffer
178 * Used for the primary processor to communcate with the console
179 * of secondary processors.
180 */
181struct iccb {
182    uint iccb_rxlen;		/* receive length in bytes      */
183    uint iccb_txlen;		/* transmit length in bytes     */
184    char iccb_rxbuf[80];	/* receive buffer               */
185    char iccb_txbuf[80];	/* transmit buffer              */
186};
187
188/*
189 * The per-cpu portion of the Alpha HWRPB.
190 * Note that the main portion of the HWRPB is of variable size,
191 * hence this must be a separate structure.
192 *
193 */
194struct rpb_percpu {
195    struct bootpcb rpb_pcb;	/* 000: boot/restart HWPCB */
196    long rpb_state;		/* 080: per-cpu state bits */
197    long rpb_palmem;		/* 088: palcode memory length */
198    long rpb_palscratch;	/* 090: palcode scratch length */
199    long rpb_palmem_addr;	/* 098: phys addr of palcode mem space */
200    long rpb_palscratch_addr;	/* 0A0: phys addr of palcode scratch space */
201    long rpb_palrev;		/* 0A8: PALcode rev required */
202    long rpb_proctype;		/* 0B0: processor type */
203    long rpb_procvar;		/* 0B8: processor variation */
204    long rpb_procrev;		/* 0C0: processor revision */
205    char rpb_procsn[16];	/* 0C8: proc serial num: 10 ascii chars */
206    long rpb_logout;		/* 0D8: phys addr of logout area */
207    long rpb_logout_len;	/* 0E0: length in bytes of logout area */
208    long rpb_haltpb;		/* 0E8: halt pcb base */
209    long rpb_haltpc;		/* 0F0: halt pc */
210    long rpb_haltps;		/* 0F8: halt ps */
211    long rpb_haltal;		/* 100: halt arg list (R25) */
212    long rpb_haltra;		/* 108: halt return address (R26) */
213    long rpb_haltpv;		/* 110: halt procedure value (R27) */
214    long rpb_haltcode;		/* 118: reason for halt */
215    long rpb_software;		/* 120: for software */
216    struct iccb	rpb_iccb;       /* 128: inter-console communications buffer */
217    long rpb_palrev_avail[16];	/* 1D0: PALcode revs available */
218    long rpb_pcrsvd[6];		/* 250: reserved for arch use */
219/* the dump stack grows from the end of the rpb page not to reach here */
220};
221
222/* The firmware revision is in the (unused) first entry of palrevs available */
223#define rpb_firmrev rpb_palrev_avail[0]
224
225/*
226 * The memory cluster descriptor.
227 */
228struct rpb_cluster {
229    long rpb_pfn;		/* 000: starting PFN of this cluster */
230    long rpb_pfncount;		/* 008: count of PFNs in this cluster */
231    long rpb_pfntested;		/* 010: count of tested PFNs in cluster */
232    long rpb_va;		/* 018: va of bitmap */
233    long rpb_pa;		/* 020: pa of bitmap */
234    long rpb_checksum;		/* 028: checksum of bitmap */
235    long rpb_usage;		/* 030: usage of cluster */
236};
237#define CLUSTER_USAGE_OS	((long)0)
238#define CLUSTER_USAGE_PAL	((long)1)
239#define CLUSTER_USAGE_NVRAM	((long)2)
240
241/*
242 * The "memory descriptor table" portion of the HWRPB.
243 * Note that the main portion of the HWRPB is of variable size and there is a
244 * variable number of per-cpu slots, hence this must be a separate structure.
245 * Also note that the memory descriptor table contains a fixed portion plus
246 * a variable number of "memory cluster descriptors" (one for each "cluster"
247 * of memory).
248 */
249struct rpb_mdt {
250    long rpb_checksum;		/* 000: checksum of entire mem desc table */
251    long rpb_impaddr;		/* 008: PA of implementation dep info */
252    long rpb_numcl;		/* 010: number of clusters */
253    struct rpb_cluster rpb_cluster[1];	/* first instance of a cluster */
254};
255
256/*
257 * The "Console Terminal Block" portion of the HWRPB, for serial line
258 * UART console device.
259 */
260struct ctb_tt {
261    long ctb_type;		/* 000: console type */
262    long ctb_unit;		/* 008: console unit */
263    long ctb_resv;		/* 010: reserved */
264    long ctb_length;		/* 018: byte length of device dep portion */
265    long ctb_csr;		/* 020: CSR Address */
266    long ctb_tivec;		/* 028: <63>=tie; interrupt vector */
267    long ctb_rivec;		/* 030: <63>=rie; interrupt vector */
268    long ctb_baud;		/* 038: baud rate */
269    long ctb_put_sts;		/* 040: PUTS callback extended status */
270    long ctb_get_sts;		/* 048: GETS callback extended status */
271    long ctb_rsvd[1];		/* 050: reserved for console use */
272};
273
274/*
275 * The "Console Terminal Block" portion of the HWRPB.
276 */
277struct rpb_ctb {
278    long rpb_type;		/* 000: console type */
279    long rpb_unit;		/* 008: console unit */
280    long rpb_resv;		/* 010: reserved */
281    long rpb_length;		/* 018: byte length of device dep portion */
282    long rpb_first;		/* 000: first field of device dep portion */
283};
284
285/*
286 * The physical/virtual map for the console routine block.
287 */
288struct rpb_map {
289    long rpb_virt;		/* virtual address for map entry */
290    long rpb_phys;		/* phys address for map entry */
291    long rpb_pgcount;		/* page count for map entry */
292};
293
294/*
295 * The "Console Routine Block" portion of the HWRPB.
296 * Note: the "offsets" are all relative to the start of the HWRPB (HWRPB_ADDR).
297 */
298struct rpb_crb {
299    long rpb_va_disp;		/* va of call-back dispatch rtn */
300    long rpb_pa_disp;		/* pa of call-back dispatch rtn */
301    long rpb_va_fixup;		/* va of call-back fixup rtn */
302    long rpb_pa_fixup;		/* pa of call-back fixup rtn */
303    long rpb_num;		/* number of entries in phys/virt map */
304    long rpb_mapped_pages;	/* Number of pages to be mapped */
305    struct rpb_map rpb_map[1];	/* first instance of a map entry */
306};
307
308/*
309 * These macros define where within the HWRPB the CTB and CRB are located.
310 */
311#define CTB_SETUP \
312    ((struct rpb_ctb *) ((long)hwrpb_addr + (long)(hwrpb_addr->rpb_ctb_off)))
313
314#define CRB_SETUP \
315    ((struct rpb_crb *) ((long)hwrpb_addr + (long)(hwrpb_addr->rpb_crb_off)))
316
317/*
318 * The "Dynamic System Recognition" portion of the HWRPB.
319 * It is used to obtain the platform specific data need to allow
320 * the platform define the platform name, the platform SMM and LURT
321 * data for software licensing
322 */
323struct rpb_dsr {
324    long rpb_smm;		/* SMM nubber used by LMF	*/
325    ulong rpb_lurt_off;		/* offset to LURT table		*/
326    ulong rpb_sysname_off;	/* offset to sysname char count	*/
327    int	lurt[10];		/* XXM has one LURT entry	*/
328};
329