rpb.h revision 8012
18012Ssaidi@eecs.umich.edu/* 28012Ssaidi@eecs.umich.eduCopyright 1990 Hewlett-Packard Development Company, L.P. 38012Ssaidi@eecs.umich.edu 48012Ssaidi@eecs.umich.eduPermission is hereby granted, free of charge, to any person obtaining a copy of 58012Ssaidi@eecs.umich.eduthis software and associated documentation files (the "Software"), to deal in 68012Ssaidi@eecs.umich.eduthe Software without restriction, including without limitation the rights to 78012Ssaidi@eecs.umich.eduuse, copy, modify, merge, publish, distribute, sublicense, and/or sell copies 88012Ssaidi@eecs.umich.eduof the Software, and to permit persons to whom the Software is furnished to do 98012Ssaidi@eecs.umich.eduso, subject to the following conditions: 108012Ssaidi@eecs.umich.edu 118012Ssaidi@eecs.umich.eduThe above copyright notice and this permission notice shall be included in all 128012Ssaidi@eecs.umich.educopies or substantial portions of the Software. 138012Ssaidi@eecs.umich.edu 148012Ssaidi@eecs.umich.eduTHE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 158012Ssaidi@eecs.umich.eduIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 168012Ssaidi@eecs.umich.eduFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 178012Ssaidi@eecs.umich.eduAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 188012Ssaidi@eecs.umich.eduLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 198012Ssaidi@eecs.umich.eduOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 208012Ssaidi@eecs.umich.eduSOFTWARE. 218012Ssaidi@eecs.umich.edu*/ 228012Ssaidi@eecs.umich.edu 237977Shsul@eecs.umich.edu/* 247977Shsul@eecs.umich.edu * "@(#)rpb.h 9.2 (ULTRIX/OSF) 10/30/91" 257977Shsul@eecs.umich.edu */ 267977Shsul@eecs.umich.edu/* 277977Shsul@eecs.umich.edu * Defines for the architected startup addresses. 287977Shsul@eecs.umich.edu */ 297977Shsul@eecs.umich.edu 307977Shsul@eecs.umich.edu#define HWRPB_ADDR 0x10000000 /* 256 MB */ 317977Shsul@eecs.umich.edu#define BOOT_ADDR 0x20000000 /* 512 MB */ 327977Shsul@eecs.umich.edu#define PGTBL_ADDR 0x40000000 /* 1 GB */ 337977Shsul@eecs.umich.edu 347977Shsul@eecs.umich.edu/* 357977Shsul@eecs.umich.edu * Values for the "haltcode" field in the per-cpu portion of the HWRPB 367977Shsul@eecs.umich.edu * 377977Shsul@eecs.umich.edu * Bit defines for the "sysvar" field in the HWRPB. 387977Shsul@eecs.umich.edu * Each platform has different values for SYSBOARD and IOBOARD bits. 397977Shsul@eecs.umich.edu */ 407977Shsul@eecs.umich.edu#define HALT_PWRUP 0 /* power up */ 417977Shsul@eecs.umich.edu#define HALT_OPR 1 /* operator issued halt cmd */ 427977Shsul@eecs.umich.edu#define HALT_KSTK 2 /* kernel stack not valid */ 437977Shsul@eecs.umich.edu#define HALT_SCBB 3 /* invalid SCBB */ 447977Shsul@eecs.umich.edu#define HALT_PTBR 4 /* invalid PTBR */ 457977Shsul@eecs.umich.edu#define HALT_EXE 5 /* kernel executed halt instruction */ 467977Shsul@eecs.umich.edu#define HALT_DBLE 6 /* double error abort */ 477977Shsul@eecs.umich.edu 487977Shsul@eecs.umich.edu/* 497977Shsul@eecs.umich.edu * Bit defines for the "state" field in the per-cpu portion of the HWRPB 507977Shsul@eecs.umich.edu */ 517977Shsul@eecs.umich.edu#define STATE_BIP 0x00000001 /* bootstrap in progress */ 527977Shsul@eecs.umich.edu#define STATE_RC 0x00000002 /* restart capable */ 537977Shsul@eecs.umich.edu#define STATE_PA 0x00000004 /* processor available to OS */ 547977Shsul@eecs.umich.edu#define STATE_PP 0x00000008 /* processor present */ 557977Shsul@eecs.umich.edu#define STATE_OH 0x00000010 /* operator halted */ 567977Shsul@eecs.umich.edu#define STATE_CV 0x00000020 /* context valid */ 577977Shsul@eecs.umich.edu#define STATE_PV 0x00000040 /* PALcode valid */ 587977Shsul@eecs.umich.edu#define STATE_PMV 0x00000080 /* PALcode memory valid */ 597977Shsul@eecs.umich.edu#define STATE_PL 0x00000100 /* PALcode loaded */ 607977Shsul@eecs.umich.edu#define STATE_HALT_MASK 0x00ff0000 /* Mask for Halt Requested field */ 617977Shsul@eecs.umich.edu#define STATE_DEFAULT 0x00000000 /* Default (no specific action) */ 627977Shsul@eecs.umich.edu#define STATE_SVRS_TERM 0x00010000 /* SAVE_TERM/RESTORE_TERM Exit */ 637977Shsul@eecs.umich.edu#define STATE_COLD_BOOT 0x00020000 /* Cold Bootstrap Requested */ 647977Shsul@eecs.umich.edu#define STATE_WARM_BOOT 0x00030000 /* Warm Bootstrap Requested */ 657977Shsul@eecs.umich.edu#define STATE_HALT 0x00040000 /* Remain halted (no restart) */ 667977Shsul@eecs.umich.edu 677977Shsul@eecs.umich.edu 687977Shsul@eecs.umich.edu#define SV_PF_RSVD 0x00000000 /* RESERVED */ 697977Shsul@eecs.umich.edu#define SV_RESERVED 0x00000000 /* All STS bits; zero for backward compat. */ 707977Shsul@eecs.umich.edu#define SV_MPCAP 0x00000001 /* MP capable */ 717977Shsul@eecs.umich.edu#define SV_PF_UNITED 0x00000020 /* United */ 727977Shsul@eecs.umich.edu#define SV_PF_SEPARATE 0x00000040 /* Separate */ 737977Shsul@eecs.umich.edu#define SV_PF_FULLBB 0x00000060 /* Full battery backup */ 747977Shsul@eecs.umich.edu#define SV_POWERFAIL 0x000000e0 /* Powerfail implementation */ 757977Shsul@eecs.umich.edu#define SV_PF_RESTART 0x00000100 /* Powerfail restart */ 767977Shsul@eecs.umich.edu 777977Shsul@eecs.umich.edu#define SV_GRAPHICS 0x00000200 /* Embedded graphics processor */ 787977Shsul@eecs.umich.edu 797977Shsul@eecs.umich.edu#define SV_STS_MASK 0x0000fc00 /* STS bits - system and I/O board */ 807977Shsul@eecs.umich.edu#define SV_SANDPIPER 0x00000400 /* others define system platforms. */ 817977Shsul@eecs.umich.edu#define SV_FLAMINGO 0x00000800 /* STS BIT SETTINGS */ 827977Shsul@eecs.umich.edu#define SV_HOTPINK 0x00000c00 /* STS BIT SETTINGS */ 837977Shsul@eecs.umich.edu#define SV_FLAMINGOPLUS 0x00001000 /* STS BIT SETTINGS */ 847977Shsul@eecs.umich.edu#define SV_ULTRA 0x00001400 /* STS BIT SETTINGS */ 857977Shsul@eecs.umich.edu#define SV_SANDPLUS 0x00001800 /* STS BIT SETTINGS */ 867977Shsul@eecs.umich.edu#define SV_SANDPIPER45 0x00001c00 /* STS BIT SETTINGS */ 877977Shsul@eecs.umich.edu#define SV_FLAMINGO45 0x00002000 /* STS BIT SETTINGS */ 887977Shsul@eecs.umich.edu 897977Shsul@eecs.umich.edu#define SV_SABLE 0x00000400 /* STS BIT SETTINGS */ 907977Shsul@eecs.umich.edu 917977Shsul@eecs.umich.edu#define SV_KN20AA 0x00000400 /* STS BIT SETTINGS */ 927977Shsul@eecs.umich.edu 937977Shsul@eecs.umich.edu/* 947977Shsul@eecs.umich.edu * Values for the "console type" field in the CTB portion of the HWRPB 957977Shsul@eecs.umich.edu */ 967977Shsul@eecs.umich.edu#define CONS_NONE 0 /* no console present */ 977977Shsul@eecs.umich.edu#define CONS_SRVC 1 /* console is service processor */ 987977Shsul@eecs.umich.edu#define CONS_DZ 2 /* console is dz/dl VT device */ 997977Shsul@eecs.umich.edu#define CONS_GRPH 3 /* cons is graphics dev w/ dz/dl keybd*/ 1007977Shsul@eecs.umich.edu#define CONS_REM 4 /* cons is remote, protocal enet/MOP */ 1017977Shsul@eecs.umich.edu 1027977Shsul@eecs.umich.edu/* 1037977Shsul@eecs.umich.edu * PALcode variants that we're interested in. 1047977Shsul@eecs.umich.edu * Used as indices into the "palrev_avail" array in the per-cpu portion 1057977Shsul@eecs.umich.edu * of the HWRPB. 1067977Shsul@eecs.umich.edu */ 1077977Shsul@eecs.umich.edu#define PALvar_reserved 0 1087977Shsul@eecs.umich.edu#define PALvar_OpenVMS 1 1097977Shsul@eecs.umich.edu#define PALvar_OSF1 2 1107977Shsul@eecs.umich.edu 1117977Shsul@eecs.umich.edu#include <sys/types.h> 1127977Shsul@eecs.umich.edu/* 1137977Shsul@eecs.umich.edu * The Alpha restart parameter block, which is a page or 2 in low memory 1147977Shsul@eecs.umich.edu */ 1157977Shsul@eecs.umich.edustruct rpb { 1167977Shsul@eecs.umich.edu struct rpb *rpb_selfref; /* 000: physical self-reference */ 1177977Shsul@eecs.umich.edu long rpb_string; /* 008: contains string "HWRPB" */ 1187977Shsul@eecs.umich.edu long rpb_vers; /* 010: HWRPB version number */ 1197977Shsul@eecs.umich.edu u_long rpb_size; /* 018: bytes in RPB perCPU CTB CRB MEMDSC */ 1207977Shsul@eecs.umich.edu u_long rpb_cpuid; /* 020: primary cpu id */ 1217977Shsul@eecs.umich.edu u_long rpb_pagesize; /* 028: page size in bytes */ 1227977Shsul@eecs.umich.edu u_long rpb_addrbits; /* 030: number of phys addr bits */ 1237977Shsul@eecs.umich.edu u_long rpb_maxasn; /* 038: max valid ASN */ 1247977Shsul@eecs.umich.edu char rpb_ssn[16]; /* 040: system serial num: 10 ascii chars */ 1257977Shsul@eecs.umich.edu u_long rpb_systype; /* 050: system type */ 1267977Shsul@eecs.umich.edu long rpb_sysvar; /* 058: system variation */ 1277977Shsul@eecs.umich.edu long rpb_sysrev; /* 060: system revision */ 1287977Shsul@eecs.umich.edu u_long rpb_clock; /* 068: scaled interval clock intr freq */ 1297977Shsul@eecs.umich.edu u_long rpb_counter; /* 070: cycle counter frequency */ 1307977Shsul@eecs.umich.edu u_long rpb_vptb; /* 078: virtual page table base */ 1317977Shsul@eecs.umich.edu long rpb_res1; /* 080: reserved */ 1327977Shsul@eecs.umich.edu u_long rpb_trans_off; /* 088: offset to translation buffer hint */ 1337977Shsul@eecs.umich.edu u_long rpb_numprocs; /* 090: number of processor slots */ 1347977Shsul@eecs.umich.edu u_long rpb_slotsize; /* 098: per-cpu slot size */ 1357977Shsul@eecs.umich.edu u_long rpb_percpu_off; /* 0A0: offset to per_cpu slots */ 1367977Shsul@eecs.umich.edu u_long rpb_num_ctb; /* 0A8: number of CTBs */ 1377977Shsul@eecs.umich.edu u_long rpb_ctb_size; /* 0B0: bytes in largest CTB */ 1387977Shsul@eecs.umich.edu u_long rpb_ctb_off; /* 0B8: offset to CTB (cons term block) */ 1397977Shsul@eecs.umich.edu u_long rpb_crb_off; /* 0C0: offset to CRB (cons routine block) */ 1407977Shsul@eecs.umich.edu u_long rpb_mdt_off; /* 0C8: offset to memory descriptor table */ 1417977Shsul@eecs.umich.edu u_long rpb_config_off; /* 0D0: offset to config data block */ 1427977Shsul@eecs.umich.edu u_long rpb_fru_off; /* 0D8: offset to FRU table */ 1437977Shsul@eecs.umich.edu void (*rpb_saveterm)(); /* 0E0: virt addr of save term routine */ 1447977Shsul@eecs.umich.edu long rpb_saveterm_pv; /* 0E8: proc value for save term routine */ 1457977Shsul@eecs.umich.edu void (*rpb_rstrterm)(); /* 0F0: virt addr of restore term routine */ 1467977Shsul@eecs.umich.edu long rpb_rstrterm_pv; /* 0F8: proc value for restore term routine */ 1477977Shsul@eecs.umich.edu void (*rpb_restart)(); /* 100: virt addr of CPU restart routine */ 1487977Shsul@eecs.umich.edu long rpb_restart_pv; /* 108: proc value for CPU restart routine */ 1497977Shsul@eecs.umich.edu long rpb_software; /* 110: used to determine presence of kdebug */ 1507977Shsul@eecs.umich.edu long rpb_hardware; /* 118: reserved for hardware */ 1517977Shsul@eecs.umich.edu long rpb_checksum; /* 120: checksum of prior entries in rpb */ 1527977Shsul@eecs.umich.edu long rpb_rxrdy; /* 128: receive ready bitmask */ 1537977Shsul@eecs.umich.edu long rpb_txrdy; /* 130: transmit ready bitmask */ 1547977Shsul@eecs.umich.edu u_long rpb_dsr_off; /* 138: Dynamic System Recog. offset */ 1557977Shsul@eecs.umich.edu}; 1567977Shsul@eecs.umich.edu 1577977Shsul@eecs.umich.edu#define rpb_kdebug rpb_software 1587977Shsul@eecs.umich.edu 1597977Shsul@eecs.umich.edu#define OSF_HWRPB_ADDR ((vm_offset_t)(-1L << 23)) 1607977Shsul@eecs.umich.edu 1617977Shsul@eecs.umich.edu/* 1627977Shsul@eecs.umich.edu * This is the format for the boot/restart HWPCB. It must match the 1637977Shsul@eecs.umich.edu * initial fields of the pcb structure as defined in pcb.h, but must 1647977Shsul@eecs.umich.edu * additionally contain the appropriate amount of padding to line up 1657977Shsul@eecs.umich.edu * with formats used by other palcode types. 1667977Shsul@eecs.umich.edu */ 1677977Shsul@eecs.umich.edustruct bootpcb { 1687977Shsul@eecs.umich.edu long rpb_ksp; /* 000: kernel stack pointer */ 1697977Shsul@eecs.umich.edu long rpb_usp; /* 008: user stack pointer */ 1707977Shsul@eecs.umich.edu long rpb_ptbr; /* 010: page table base register */ 1717977Shsul@eecs.umich.edu int rpb_cc; /* 018: cycle counter */ 1727977Shsul@eecs.umich.edu int rpb_asn; /* 01C: address space number */ 1737977Shsul@eecs.umich.edu long rpb_proc_uniq; /* 020: proc/thread unique value */ 1747977Shsul@eecs.umich.edu long rpb_fen; /* 028: floating point enable */ 1757977Shsul@eecs.umich.edu long rpb_palscr[2]; /* 030: pal scratch area */ 1767977Shsul@eecs.umich.edu long rpb_pcbpad[8]; /* 040: padding for fixed size */ 1777977Shsul@eecs.umich.edu}; 1787977Shsul@eecs.umich.edu 1797977Shsul@eecs.umich.edu/* 1807977Shsul@eecs.umich.edu * Inter-Console Communications Buffer 1817977Shsul@eecs.umich.edu * Used for the primary processor to communcate with the console 1827977Shsul@eecs.umich.edu * of secondary processors. 1837977Shsul@eecs.umich.edu */ 1847977Shsul@eecs.umich.edustruct iccb { 1857977Shsul@eecs.umich.edu u_int iccb_rxlen; /* receive length in bytes */ 1867977Shsul@eecs.umich.edu u_int iccb_txlen; /* transmit length in bytes */ 1877977Shsul@eecs.umich.edu char iccb_rxbuf[80]; /* receive buffer */ 1887977Shsul@eecs.umich.edu char iccb_txbuf[80]; /* transmit buffer */ 1897977Shsul@eecs.umich.edu}; 1907977Shsul@eecs.umich.edu 1917977Shsul@eecs.umich.edu/* 1927977Shsul@eecs.umich.edu * The per-cpu portion of the Alpha HWRPB. 1937977Shsul@eecs.umich.edu * Note that the main portion of the HWRPB is of variable size, 1947977Shsul@eecs.umich.edu * hence this must be a separate structure. 1957977Shsul@eecs.umich.edu * 1967977Shsul@eecs.umich.edu */ 1977977Shsul@eecs.umich.edustruct rpb_percpu { 1987977Shsul@eecs.umich.edu struct bootpcb rpb_pcb; /* 000: boot/restart HWPCB */ 1997977Shsul@eecs.umich.edu long rpb_state; /* 080: per-cpu state bits */ 2007977Shsul@eecs.umich.edu long rpb_palmem; /* 088: palcode memory length */ 2017977Shsul@eecs.umich.edu long rpb_palscratch; /* 090: palcode scratch length */ 2027977Shsul@eecs.umich.edu long rpb_palmem_addr; /* 098: phys addr of palcode mem space */ 2037977Shsul@eecs.umich.edu long rpb_palscratch_addr; /* 0A0: phys addr of palcode scratch space */ 2047977Shsul@eecs.umich.edu long rpb_palrev; /* 0A8: PALcode rev required */ 2057977Shsul@eecs.umich.edu long rpb_proctype; /* 0B0: processor type */ 2067977Shsul@eecs.umich.edu long rpb_procvar; /* 0B8: processor variation */ 2077977Shsul@eecs.umich.edu long rpb_procrev; /* 0C0: processor revision */ 2087977Shsul@eecs.umich.edu char rpb_procsn[16]; /* 0C8: proc serial num: 10 ascii chars */ 2097977Shsul@eecs.umich.edu long rpb_logout; /* 0D8: phys addr of logout area */ 2107977Shsul@eecs.umich.edu long rpb_logout_len; /* 0E0: length in bytes of logout area */ 2117977Shsul@eecs.umich.edu long rpb_haltpb; /* 0E8: halt pcb base */ 2127977Shsul@eecs.umich.edu long rpb_haltpc; /* 0F0: halt pc */ 2137977Shsul@eecs.umich.edu long rpb_haltps; /* 0F8: halt ps */ 2147977Shsul@eecs.umich.edu long rpb_haltal; /* 100: halt arg list (R25) */ 2157977Shsul@eecs.umich.edu long rpb_haltra; /* 108: halt return address (R26) */ 2167977Shsul@eecs.umich.edu long rpb_haltpv; /* 110: halt procedure value (R27) */ 2177977Shsul@eecs.umich.edu long rpb_haltcode; /* 118: reason for halt */ 2187977Shsul@eecs.umich.edu long rpb_software; /* 120: for software */ 2197977Shsul@eecs.umich.edu struct iccb rpb_iccb; /* 128: inter-console communications buffer */ 2207977Shsul@eecs.umich.edu long rpb_palrev_avail[16];/* 1D0: PALcode revs available */ 2217977Shsul@eecs.umich.edu long rpb_pcrsvd[6]; /* 250: reserved for arch use */ 2227977Shsul@eecs.umich.edu/* the dump stack grows from the end of the rpb page not to reach here */ 2237977Shsul@eecs.umich.edu}; 2247977Shsul@eecs.umich.edu 2257977Shsul@eecs.umich.edu/* The firmware revision is in the (unused) first entry of palrevs available */ 2267977Shsul@eecs.umich.edu#define rpb_firmrev rpb_palrev_avail[0] 2277977Shsul@eecs.umich.edu 2287977Shsul@eecs.umich.edu/* 2297977Shsul@eecs.umich.edu * The memory cluster descriptor. 2307977Shsul@eecs.umich.edu */ 2317977Shsul@eecs.umich.edustruct rpb_cluster { 2327977Shsul@eecs.umich.edu long rpb_pfn; /* 000: starting PFN of this cluster */ 2337977Shsul@eecs.umich.edu long rpb_pfncount; /* 008: count of PFNs in this cluster */ 2347977Shsul@eecs.umich.edu long rpb_pfntested; /* 010: count of tested PFNs in cluster */ 2357977Shsul@eecs.umich.edu long rpb_va; /* 018: va of bitmap */ 2367977Shsul@eecs.umich.edu long rpb_pa; /* 020: pa of bitmap */ 2377977Shsul@eecs.umich.edu long rpb_checksum; /* 028: checksum of bitmap */ 2387977Shsul@eecs.umich.edu long rpb_usage; /* 030: usage of cluster */ 2397977Shsul@eecs.umich.edu}; 2407977Shsul@eecs.umich.edu#define CLUSTER_USAGE_OS ((long)0) 2417977Shsul@eecs.umich.edu#define CLUSTER_USAGE_PAL ((long)1) 2427977Shsul@eecs.umich.edu#define CLUSTER_USAGE_NVRAM ((long)2) 2437977Shsul@eecs.umich.edu 2447977Shsul@eecs.umich.edu/* 2457977Shsul@eecs.umich.edu * The "memory descriptor table" portion of the HWRPB. 2467977Shsul@eecs.umich.edu * Note that the main portion of the HWRPB is of variable size and there is a 2477977Shsul@eecs.umich.edu * variable number of per-cpu slots, hence this must be a separate structure. 2487977Shsul@eecs.umich.edu * Also note that the memory descriptor table contains a fixed portion plus 2497977Shsul@eecs.umich.edu * a variable number of "memory cluster descriptors" (one for each "cluster" 2507977Shsul@eecs.umich.edu * of memory). 2517977Shsul@eecs.umich.edu */ 2527977Shsul@eecs.umich.edustruct rpb_mdt { 2537977Shsul@eecs.umich.edu long rpb_checksum; /* 000: checksum of entire mem desc table */ 2547977Shsul@eecs.umich.edu long rpb_impaddr; /* 008: PA of implementation dep info */ 2557977Shsul@eecs.umich.edu long rpb_numcl; /* 010: number of clusters */ 2567977Shsul@eecs.umich.edu struct rpb_cluster rpb_cluster[1]; /* first instance of a cluster */ 2577977Shsul@eecs.umich.edu}; 2587977Shsul@eecs.umich.edu 2597977Shsul@eecs.umich.edu/* 2607977Shsul@eecs.umich.edu * The "Console Terminal Block" portion of the HWRPB, for serial line 2617977Shsul@eecs.umich.edu * UART console device. 2627977Shsul@eecs.umich.edu */ 2637977Shsul@eecs.umich.edustruct ctb_tt { 2647977Shsul@eecs.umich.edu long ctb_type; /* 000: console type */ 2657977Shsul@eecs.umich.edu long ctb_unit; /* 008: console unit */ 2667977Shsul@eecs.umich.edu long ctb_resv; /* 010: reserved */ 2677977Shsul@eecs.umich.edu long ctb_length; /* 018: byte length of device dep */ 2687977Shsul@eecs.umich.edu /* portion */ 2697977Shsul@eecs.umich.edu long ctb_csr; /* 020: CSR Address */ 2707977Shsul@eecs.umich.edu long ctb_tivec; /* 028: <63>=tie; interrupt vector */ 2717977Shsul@eecs.umich.edu long ctb_rivec; /* 030: <63>=rie; interrupt vector */ 2727977Shsul@eecs.umich.edu long ctb_baud; /* 038: baud rate */ 2737977Shsul@eecs.umich.edu long ctb_put_sts; /* 040: PUTS callback extended status */ 2747977Shsul@eecs.umich.edu long ctb_get_sts; /* 048: GETS callback extended status */ 2757977Shsul@eecs.umich.edu long ctb_rsvd[1]; /* 050: reserved for console use */ 2767977Shsul@eecs.umich.edu}; 2777977Shsul@eecs.umich.edu 2787977Shsul@eecs.umich.edu/* 2797977Shsul@eecs.umich.edu * The "Console Terminal Block" portion of the HWRPB. 2807977Shsul@eecs.umich.edu */ 2817977Shsul@eecs.umich.edustruct rpb_ctb { 2827977Shsul@eecs.umich.edu long rpb_type; /* 000: console type */ 2837977Shsul@eecs.umich.edu long rpb_unit; /* 008: console unit */ 2847977Shsul@eecs.umich.edu long rpb_resv; /* 010: reserved */ 2857977Shsul@eecs.umich.edu long rpb_length; /* 018: byte length of device dep portion */ 2867977Shsul@eecs.umich.edu long rpb_first; /* 000: first field of device dep portion */ 2877977Shsul@eecs.umich.edu}; 2887977Shsul@eecs.umich.edu 2897977Shsul@eecs.umich.edu/* 2907977Shsul@eecs.umich.edu * The physical/virtual map for the console routine block. 2917977Shsul@eecs.umich.edu */ 2927977Shsul@eecs.umich.edustruct rpb_map { 2937977Shsul@eecs.umich.edu long rpb_virt; /* virtual address for map entry */ 2947977Shsul@eecs.umich.edu long rpb_phys; /* phys address for map entry */ 2957977Shsul@eecs.umich.edu long rpb_pgcount; /* page count for map entry */ 2967977Shsul@eecs.umich.edu}; 2977977Shsul@eecs.umich.edu 2987977Shsul@eecs.umich.edu/* 2997977Shsul@eecs.umich.edu * The "Console Routine Block" portion of the HWRPB. 3007977Shsul@eecs.umich.edu * Note: the "offsets" are all relative to the start of the HWRPB (HWRPB_ADDR). 3017977Shsul@eecs.umich.edu */ 3027977Shsul@eecs.umich.edustruct rpb_crb { 3037977Shsul@eecs.umich.edu long rpb_va_disp; /* va of call-back dispatch rtn */ 3047977Shsul@eecs.umich.edu long rpb_pa_disp; /* pa of call-back dispatch rtn */ 3057977Shsul@eecs.umich.edu long rpb_va_fixup; /* va of call-back fixup rtn */ 3067977Shsul@eecs.umich.edu long rpb_pa_fixup; /* pa of call-back fixup rtn */ 3077977Shsul@eecs.umich.edu long rpb_num; /* number of entries in phys/virt map */ 3087977Shsul@eecs.umich.edu long rpb_mapped_pages; /* Number of pages to be mapped */ 3097977Shsul@eecs.umich.edu struct rpb_map rpb_map[1]; /* first instance of a map entry */ 3107977Shsul@eecs.umich.edu}; 3117977Shsul@eecs.umich.edu 3127977Shsul@eecs.umich.edu/* 3137977Shsul@eecs.umich.edu * These macros define where within the HWRPB the CTB and CRB are located. 3147977Shsul@eecs.umich.edu */ 3157977Shsul@eecs.umich.edu#define CTB_SETUP ((struct rpb_ctb *) ((long)hwrpb_addr + \ 3167977Shsul@eecs.umich.edu (long)(hwrpb_addr->rpb_ctb_off))) 3177977Shsul@eecs.umich.edu#define CRB_SETUP ((struct rpb_crb *) ((long)hwrpb_addr + \ 3187977Shsul@eecs.umich.edu (long)(hwrpb_addr->rpb_crb_off))) 3197977Shsul@eecs.umich.edu 3207977Shsul@eecs.umich.edu/* 3217977Shsul@eecs.umich.edu * The "Dynamic System Recognition" portion of the HWRPB. 3227977Shsul@eecs.umich.edu * It is used to obtain the platform specific data need to allow 3237977Shsul@eecs.umich.edu * the platform define the platform name, the platform SMM and LURT 3247977Shsul@eecs.umich.edu * data for software licensing 3257977Shsul@eecs.umich.edu */ 3267977Shsul@eecs.umich.edustruct rpb_dsr { 3277977Shsul@eecs.umich.edu long rpb_smm; /* SMM nubber used by LMF */ 3287977Shsul@eecs.umich.edu u_long rpb_lurt_off; /* offset to LURT table */ 3297977Shsul@eecs.umich.edu u_long rpb_sysname_off; /* offset to sysname char count */ 3307977Shsul@eecs.umich.edu int lurt[10]; /* XXM has one LURT entry */ 3317977Shsul@eecs.umich.edu}; 332