ev5_impure.h revision 7997:b91bdbee66c3 
1#ifndef EV5_IMPURE_INCLUDED
2#define EV5_IMPURE_INCLUDED
3
4/*
5// This uses the Hudson file format from "impure.h" but with the fields from
6// the distrubuted palcode "ev5_impure.sdl" .. pboyle Nov/95
7
8//orig  file:	impure.sdl
9//orig
10//orig  Abstract:	PAL impure scratch area and logout area data structure definitions for
11//orig 		Alpha firmware.
12//orig
13//orig
14//orig  module	$pal_impure;
15//orig
16//orig  Edit   Date     Who       Description
17//orig  ---- ---------  ---  ---------------------
18//orig     1   7-Jul-93 JEM   Initial Entry
19//orig     2  18-nov-93 JEM   Add shadow bc_ctl and pmctr_ctl to impure area
20//orig 			 Delete mvptbr
21//orig 			 Calculate pal$logout from end of impure area
22//orig     3   6-dec-93 JEM   Add pmctr_ctl bitfield definitions
23//orig     4   3-feb-94 JEM   Remove f31,r31 from impure area; Remove bc_ctl, pmctr_ctl;
24//orig 				add ic_perr_stat, pmctr, dc_perr_stat, sc_stat, sc_addr, sc_ctl,
25//orig 				    bc_tag_addr, ei_stat, ei_addr, fill_syn, ld_lock
26//orig     5  19-feb-94 JEM   add gpr constants, and add f31,r31 back in to be consistent with ev4
27//orig 			 add cns$ipr_offset
28//orig     6  18-apr-94 JEM   Add shadow bc_ctl and pmctr_ctl to impure area again.
29//orig     7  18-jul-94 JEM   Add bc_config shadow.   Add mchk$sys_base constant to mchk logout frame
30//orig
31//orig
32//orig     constant REVISION equals 7 prefix IMPURE$;            // Revision number of this file
33//orig
34
35** Macros for saving/restoring data to/from the PAL impure scratch
36** area.
37**
38** The console save state area is larger than the addressibility
39** of the HW_LD/ST instructions (10-bit signed byte displacement),
40** so some adjustments to the base offsets, as well as the offsets
41** within each base region, are necessary.
42**
43** The console save state area is divided into two segments; the
44** CPU-specific segment and the platform-specific segment.  The
45** state that is saved in the CPU-specific segment includes GPRs,
46** FPRs, IPRs, halt code, MCHK flag, etc.  All other state is saved
47** in the platform-specific segment.
48**
49** The impure pointer will need to be adjusted by a different offset
50** value for each region within a given segment.  The SAVE and RESTORE
51** macros will auto-magically adjust the offsets accordingly.
52**
53*/
54#if 0
55#define SAVE_GPR(reg,offset,base) \
56        stq_p	reg, ((offset-0x200)&0x3FF)(base)
57
58#define RESTORE_GPR(reg,offset,base) \
59        ldq_p	reg, ((offset-0x200)&0x3FF)(base)
60
61
62#define SAVE_FPR(reg,offset,base) \
63        stt	reg, ((offset-0x200)&0x3FF)(base)
64
65#define RESTORE_FPR(reg,offset,base) \
66        ldt	reg, ((offset-0x200)&0x3FF)(base)
67
68#define SAVE_IPR(reg,offset,base) \
69        mfpr	v0, reg;	  \
70        stq_p	v0, ((offset-CNS_Q_IPR)&0x3FF)(base)
71
72#define RESTORE_IPR(reg,offset,base) \
73        ldq_p	v0, ((offset-CNS_Q_IPR)&0x3FF)(base); \
74        mtpr	v0, reg
75
76#define SAVE_SHADOW(reg,offset,base) \
77        stq_p	reg, ((offset-CNS_Q_IPR)&0x3FF)(base)
78
79#define	RESTORE_SHADOW(reg,offset,base)\
80        ldq_p	reg, ((offset-CNS_Q_IPR)&0x3FF)(base)
81#else
82//#define SEXT10(X) (((X) & 0x200) ? ((X) | 0xfffffffffffffc00) : (X))
83#define SEXT10(X) ((X) & 0x3ff)
84//#define SEXT10(X) (((X) << 55) >> 55)
85
86#define SAVE_GPR(reg,offset,base) \
87        stq_p	reg, (SEXT10(offset-0x200))(base)
88
89#define RESTORE_GPR(reg,offset,base) \
90        ldq_p	reg, (SEXT10(offset-0x200))(base)
91
92
93#define SAVE_FPR(reg,offset,base) \
94        stt	reg, (SEXT10(offset-0x200))(base)
95
96#define RESTORE_FPR(reg,offset,base) \
97        ldt	reg, (SEXT10(offset-0x200))(base)
98
99#define SAVE_IPR(reg,offset,base) \
100        mfpr	v0, reg;	  \
101        stq_p	v0, (SEXT10(offset-CNS_Q_IPR))(base)
102
103#define RESTORE_IPR(reg,offset,base) \
104        ldq_p	v0, (SEXT10(offset-CNS_Q_IPR))(base); \
105        mtpr	v0, reg
106
107#define SAVE_SHADOW(reg,offset,base) \
108        stq_p	reg, (SEXT10(offset-CNS_Q_IPR))(base)
109
110#define	RESTORE_SHADOW(reg,offset,base)\
111        ldq_p	reg, (SEXT10(offset-CNS_Q_IPR))(base)
112#endif
113/* orig  Structure of the processor-specific impure area */
114
115/* orig aggregate impure struct prefix "" tag "";
116 * orig 	cns$flag	quadword;
117 * orig 	cns$hlt		quadword;
118*/
119
120/* Define base for debug monitor compatibility */
121#define CNS_Q_BASE      0x000
122#define CNS_Q_FLAG	0x100
123#define CNS_Q_HALT	0x108
124
125
126/* orig constant (
127 * orig 	cns$r0,cns$r1,cns$r2,cns$r3,cns$r4,cns$r5,cns$r6,cns$r7,
128 * orig 	cns$r8,cns$r9,cns$r10,cns$r11,cns$r12,cns$r13,cns$r14,cns$r15,
129 * orig 	cns$r16,cns$r17,cns$r18,cns$r19,cns$r20,cns$r21,cns$r22,cns$r23,
130 * orig 	cns$r24,cns$r25,cns$r26,cns$r27,cns$r28,cns$r29,cns$r30,cns$r31
131 * orig 	) equals . increment 8 prefix "" tag "";
132 * orig 	cns$gpr	quadword dimension 32;
133*/
134/* Offset to base of saved GPR area - 32 quadword */
135#define CNS_Q_GPR	0x110
136#define cns_gpr CNS_Q_GPR
137
138/* orig constant (
139 * orig 	cns$f0,cns$f1,cns$f2,cns$f3,cns$f4,cns$f5,cns$f6,cns$f7,
140 * orig 	cns$f8,cns$f9,cns$f10,cns$f11,cns$f12,cns$f13,cns$f14,cns$f15,
141 * orig 	cns$f16,cns$f17,cns$f18,cns$f19,cns$f20,cns$f21,cns$f22,cns$f23,
142 * orig 	cns$f24,cns$f25,cns$f26,cns$f27,cns$f28,cns$f29,cns$f30,cns$f31
143 * orig 	) equals . increment 8 prefix "" tag "";
144 * orig 	cns$fpr	quadword dimension 32;
145*/
146/* Offset to base of saved FPR area - 32 quadwords */
147#define CNS_Q_FPR	0x210
148
149/* orig 	#t=.;
150 * orig 	cns$mchkflag quadword;
151*/
152#define CNS_Q_MCHK	0x310
153
154/* orig 	constant cns$pt_offset equals .;
155 * orig  constant (
156 * orig 	cns$pt0,cns$pt1,cns$pt2,cns$pt3,cns$pt4,cns$pt5,cns$pt6,
157 * orig 	cns$pt7,cns$pt8,cns$pt9,cns$pt10,cns$pt11,cns$pt12,cns$pt13,
158 * orig 	cns$pt14,cns$pt15,cns$pt16,cns$pt17,cns$pt18,cns$pt19,cns$pt20,
159 * orig 	cns$pt21,cns$pt22,cns$pt23
160 * orig 	) equals . increment 8 prefix "" tag "";
161 * orig 	cns$pt	quadword dimension 24;
162*/
163/* Offset to base of saved PALtemp area - 25 quadwords */
164#define CNS_Q_PT	0x318
165
166/* orig 	cns$shadow8	quadword;
167 * orig 	cns$shadow9	quadword;
168 * orig 	cns$shadow10	quadword;
169 * orig 	cns$shadow11	quadword;
170 * orig 	cns$shadow12	quadword;
171 * orig 	cns$shadow13	quadword;
172 * orig 	cns$shadow14	quadword;
173 * orig 	cns$shadow25	quadword;
174*/
175/* Offset to base of saved PALshadow area - 8 quadwords */
176#define CNS_Q_SHADOW	0x3D8
177
178/* Offset to base of saved IPR area */
179#define CNS_Q_IPR	0x418
180
181/* orig 	constant cns$ipr_offset equals .; */
182/* orig 	cns$exc_addr	quadword; */
183#define CNS_Q_EXC_ADDR		0x418
184/* orig 	cns$pal_base	quadword; */
185#define CNS_Q_PAL_BASE		0x420
186/* orig 	cns$mm_stat	quadword; */
187#define CNS_Q_MM_STAT		0x428
188/* orig 	cns$va		quadword; */
189#define CNS_Q_VA		0x430
190/* orig 	cns$icsr	quadword; */
191#define CNS_Q_ICSR		0x438
192/* orig 	cns$ipl		quadword; */
193#define CNS_Q_IPL		0x440
194/* orig 	cns$ps		quadword;	// Ibox current mode */
195#define CNS_Q_IPS		0x448
196/* orig 	cns$itb_asn	quadword; */
197#define CNS_Q_ITB_ASN		0x450
198/* orig 	cns$aster	quadword; */
199#define CNS_Q_ASTER		0x458
200/* orig 	cns$astrr	quadword; */
201#define CNS_Q_ASTRR		0x460
202/* orig 	cns$isr		quadword; */
203#define CNS_Q_ISR		0x468
204/* orig 	cns$ivptbr	quadword; */
205#define CNS_Q_IVPTBR		0x470
206/* orig 	cns$mcsr	quadword; */
207#define CNS_Q_MCSR		0x478
208/* orig 	cns$dc_mode	quadword; */
209#define CNS_Q_DC_MODE		0x480
210/* orig 	cns$maf_mode	quadword; */
211#define CNS_Q_MAF_MODE		0x488
212/* orig 	cns$sirr	quadword; */
213#define CNS_Q_SIRR		0x490
214/* orig 	cns$fpcsr	quadword; */
215#define CNS_Q_FPCSR		0x498
216/* orig 	cns$icperr_stat	quadword; */
217#define CNS_Q_ICPERR_STAT	0x4A0
218/* orig 	cns$pmctr	quadword; */
219#define CNS_Q_PM_CTR		0x4A8
220/* orig 	cns$exc_sum	quadword; */
221#define CNS_Q_EXC_SUM		0x4B0
222/* orig 	cns$exc_mask	quadword; */
223#define CNS_Q_EXC_MASK		0x4B8
224/* orig 	cns$intid	quadword; */
225#define CNS_Q_INT_ID		0x4C0
226/* orig 	cns$dcperr_stat quadword; */
227#define CNS_Q_DCPERR_STAT	0x4C8
228/* orig 	cns$sc_stat	quadword; */
229#define CNS_Q_SC_STAT		0x4D0
230/* orig 	cns$sc_addr	quadword; */
231#define CNS_Q_SC_ADDR		0x4D8
232/* orig 	cns$sc_ctl	quadword; */
233#define CNS_Q_SC_CTL		0x4E0
234/* orig 	cns$bc_tag_addr	quadword; */
235#define CNS_Q_BC_TAG_ADDR	0x4E8
236/* orig 	cns$ei_stat	quadword; */
237#define CNS_Q_EI_STAT		0x4F0
238/* orig 	cns$ei_addr	quadword; */
239#define CNS_Q_EI_ADDR		0x4F8
240/* orig 	cns$fill_syn	quadword; */
241#define CNS_Q_FILL_SYN		0x500
242/* orig 	cns$ld_lock	quadword; */
243#define CNS_Q_LD_LOCK		0x508
244/* orig 	cns$bc_ctl	quadword;	// shadow of on chip bc_ctl  */
245#define CNS_Q_BC_CTL		0x510
246/* orig 	cns$pmctr_ctl   quadword;	// saved frequency select info for performance monitor counter */
247#define CNS_Q_PM_CTL		0x518
248/* orig 	cns$bc_config	quadword;	// shadow of on chip bc_config */
249#define CNS_Q_BC_CFG            0x520
250
251/* orig 	constant cns$size equals .;
252 * orig
253 * orig 	constant pal$impure_common_size equals (%x0200 +7) & %xfff8;
254 * orig 	constant pal$impure_specific_size equals (.+7) & %xfff8;
255 * orig 	constant cns$mchksize equals (.+7-#t) & %xfff8;
256 * orig 	constant pal$logout_area	equals pal$impure_specific_size ;
257 * orig end impure;
258*/
259
260/* This next set of stuff came from the old code ..pb */
261#define CNS_Q_SROM_REV          0x528
262#define CNS_Q_PROC_ID           0x530
263#define CNS_Q_MEM_SIZE          0x538
264#define CNS_Q_CYCLE_CNT         0x540
265#define CNS_Q_SIGNATURE         0x548
266#define CNS_Q_PROC_MASK         0x550
267#define CNS_Q_SYSCTX            0x558
268
269
270
271#define MACHINE_CHECK_CRD_BASE 0
272#define MACHINE_CHECK_SIZE ((CNS_Q_SYSCTX + 7 - CNS_Q_MCHK) & 0xfff8)
273
274
275
276/* orig
277 * orig aggregate EV5PMCTRCTL_BITS structure fill prefix PMCTR_CTL$;
278 * orig 	SPROCESS bitfield length 1 ;
279 * orig 	FILL_0 bitfield length 3 fill tag $$;
280 * orig 	FRQ2 bitfield length 2 ;
281 * orig 	FRQ1 bitfield length 2 ;
282 * orig 	FRQ0 bitfield length 2 ;
283 * orig 	CTL2 bitfield length 2 ;
284 * orig 	CTL1 bitfield length 2 ;
285 * orig 	CTL0 bitfield length 2 ;
286 * orig 	FILL_1 bitfield length 16 fill tag $$;
287 * orig 	FILL_2 bitfield length 32 fill tag $$;
288 * orig end EV5PMCTRCTL_BITS;
289 * orig
290 * orig end_module $pal_impure;
291 * orig
292 * orig module	$pal_logout;
293 * orig
294 * orig //
295 * orig // Start definition of Corrected Error Frame
296 * orig //
297 */
298
299/*
300 * orig aggregate crd_logout struct prefix "" tag "";
301 */
302
303#ifdef SIMOS
304#define pal_logout_area 0x600
305#define mchk_crd_base  0
306#endif
307
308/* orig 	mchk$crd_flag		quadword; */
309#define mchk_crd_flag 0
310/* orig 	mchk$crd_offsets	quadword; */
311#define mchk_crd_offsets 8
312/* orig
313 * orig 	// Pal-specific information	*/
314#define mchk_crd_mchk_code 0x10
315/* orig 	mchk$crd_mchk_code	quadword;
316 * orig
317 * orig 	// CPU-specific information
318 * orig 	constant mchk$crd_cpu_base equals . ;
319 * orig 	mchk$crd_ei_addr	quadword; */
320#define mchk_crd_ei_addr 0x18
321/* orig 	mchk$crd_fill_syn	quadword; */
322#define mchk_crd_fill_syn 0x20
323/* orig 	mchk$crd_ei_stat	quadword; */
324#define mchk_crd_ei_stat 0x28
325/* orig 	mchk$crd_isr		quadword; */
326#define mchk_crd_isr 0x30
327
328/*
329 * Hacked up constants for the turbolaser build. Hope
330 * this is moreless correct
331 */
332
333#define mchk_crd_whami   0x38
334#define mchk_crd_tldev   0x40
335#define mchk_crd_tlber   0x48
336#define mchk_crd_tlesr0  0x50
337#define mchk_crd_tlesr1  0x58
338#define mchk_crd_tlesr2  0x60
339#define mchk_crd_tlesr3  0x68
340#define mchk_crd_rsvd    0x70
341
342
343#ifdef SIMOS
344/*
345 * mchk area seems different for tlaser
346 */
347
348#define mchk_crd_size   0x80
349#define mchk_mchk_base (mchk_crd_size)
350
351#define mchk_tlber      0x0
352#define mchk_tlepaerr   0x8
353#define mchk_tlepderr   0x10
354#define mchk_tlepmerr   0x18
355
356
357#endif
358
359
360/* orig
361 * orig 	// System-specific information
362 * orig 	constant mchk$crd_sys_base equals . ;
363 * orig 	constant mchk$crd_size equals (.+7) & %xfff8;
364 * orig
365 * orig end crd_logout;
366 * orig //
367 * orig // Start definition of Machine check logout Frame
368 * orig //
369 * orig aggregate logout struct prefix "" tag "";
370 * orig 	mchk$flag		quadword; */
371/* orig 	mchk$offsets		quadword; */
372/* orig
373 * orig  // Pal-specific information
374 * orig 	mchk$mchk_code		quadword; */
375/*
376
377 * orig 	mchk$pt	quadword dimension 24;
378 * orig
379 * orig  // CPU-specific information
380 * orig 	constant mchk$cpu_base equals . ;
381 * orig 	mchk$exc_addr		quadword;
382 * orig 	mchk$exc_sum		quadword;
383 * orig 	mchk$exc_mask		quadword;
384 * orig 	mchk$pal_base		quadword;
385 * orig 	mchk$isr		quadword;
386 * orig 	mchk$icsr		quadword;
387 * orig 	mchk$ic_perr_stat       quadword;
388 * orig 	mchk$dc_perr_stat	quadword;
389 * orig 	mchk$va		        quadword;
390 * orig 	mchk$mm_stat		quadword;
391 * orig 	mchk$sc_addr		quadword;
392 * orig 	mchk$sc_stat		quadword;
393 * orig 	mchk$bc_tag_addr	quadword;
394 * orig 	mchk$ei_addr		quadword;
395 * orig 	mchk$fill_syn		quadword;
396 * orig 	mchk$ei_stat		quadword;
397 * orig 	mchk$ld_lock		quadword;
398 * orig
399 * orig         // System-specific information
400 * orig
401 * orig 	constant mchk$sys_base equals . ;
402 * orig 	mchk$sys_ipr1		quadword	; // Holder for system-specific stuff
403 * orig
404 * orig 	constant mchk$size equals (.+7) & %xfff8;
405 * orig
406 * orig
407 * orig 	constant mchk$crd_base	equals 0 ;
408 * orig 	constant mchk$mchk_base	equals mchk$crd_size ;
409 * orig
410 * orig
411 * orig end logout;
412 * orig
413 * orig end_module $pal_logout;
414*/
415
416
417
418
419/* this is lingering in the old ladbx code but looks like it was from ev4 days.
420 * This was 0x160 in the old days..pb
421*/
422#define LAF_K_SIZE         MACHINE_CHECK_SIZE
423#endif
424