ev5_defs.h revision 8013:2dfcde2e9998
1/* 2 * Copyright 1995 Hewlett-Packard Development Company, L.P. 3 * 4 * Permission is hereby granted, free of charge, to any person 5 * obtaining a copy of this software and associated documentation 6 * files (the "Software"), to deal in the Software without 7 * restriction, including without limitation the rights to use, copy, 8 * modify, merge, publish, distribute, sublicense, and/or sell copies 9 * of the Software, and to permit persons to whom the Software is 10 * furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be 13 * included in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 25#ifndef EV5_DEFS_INCLUDED 26#define EV5_DEFS_INCLUDED 1 27 28// adapted from the version emailed to lance..pb Nov/95 29 30// In the definitions below, registers are annotated with one of the 31// following symbols: 32// 33// RW - The register may be read and written 34// RO - The register may only be read 35// WO - The register may only be written 36// 37// For RO and WO registers, all bits and fields within the register 38// are also read-only or write-only. For RW registers, each bit or 39// field within the register is annotated with one of the following: 40// 41// RW - The bit/field may be read and written 42// RO - The bit/field may be read; writes are ignored 43// WO - The bit/field may be written; reads return an UNPREDICTABLE result 44// WZ - The bit/field may be written; reads return a 0 45// WC - The bit/field may be read; writes cause state to clear 46// RC - The bit/field may be read, which also causes state to clear; 47// writes are ignored 48// Architecturally-defined (SRM) registers for EVMS 49 50#define pt0 320 51#define pt1 321 52#define pt2 322 53#define pt3 323 54#define pt4 324 55#define pt5 325 56#define pt6 326 57#define pt7 327 58#define pt8 328 59#define pt9 329 60#define pt10 330 61#define pt11 331 62#define pt12 332 63#define pt13 333 64#define pt14 334 65#define pt15 335 66#define pt16 336 67#define pt17 337 68#define pt18 338 69#define pt19 339 70#define pt20 340 71#define pt21 341 72#define pt22 342 73#define pt23 343 74#define cbox_ipr_offset 16777200 75#define sc_ctl 168 76#define sc_stat 232 77#define sc_addr 392 78#define sc_addr_nm 392 79#define sc_addr_fhm 392 80#define bc_ctl 296 81#define bc_config 456 82#define ei_stat 360 83#define ei_addr 328 84#define fill_syn 104 85#define bc_tag_addr 264 86#define ld_lock 488 87#define aster 266 88#define astrr 265 89#define exc_addr 267 90#define exc_sum 268 91#define exc_mask 269 92#define hwint_clr 277 93#define ic_flush_ctl 281 94#define icperr_stat 282 95#define ic_perr_stat 282 96#define ic_row_map 283 97#define icsr 280 98#define ifault_va_form 274 99#define intid 273 100#define ipl 272 101#define isr 256 102#define itb_is 263 103#define itb_asn 259 104#define itb_ia 261 105#define itb_iap 262 106#define itb_pte 258 107#define itb_pte_temp 260 108#define itb_tag 257 109#define ivptbr 275 110#define pal_base 270 111#define pmctr 284 112// this is not the register ps .. pb #define ps 271 113#define sirr 264 114#define sl_txmit 278 115#define sl_rcv 279 116#define alt_mode 524 117#define cc 525 118#define cc_ctl 526 119#define dc_flush 528 120#define dcperr_stat 530 121#define dc_test_ctl 531 122#define dc_test_tag 532 123#define dc_test_tag_temp 533 124#define dtb_asn 512 125#define dtb_cm 513 126#define dtb_ia 522 127#define dtb_iap 521 128#define dtb_is 523 129#define dtb_pte 515 130#define dtb_pte_temp 516 131#define dtb_tag 514 132#define mcsr 527 133#define dc_mode 534 134#define maf_mode 535 135#define mm_stat 517 136#define mvptbr 520 137#define va 518 138#define va_form 519 139#define ev5_srm__ps 0 140#define ev5_srm__pc 0 141#define ev5_srm__asten 0 142#define ev5_srm__astsr 0 143#define ev5_srm__ipir 0 144#define ev5_srm__ipl 0 145#define ev5_srm__mces 0 146#define ev5_srm__pcbb 0 147#define ev5_srm__prbr 0 148#define ev5_srm__ptbr 0 149#define ev5_srm__scbb 0 150#define ev5_srm__sirr 0 151#define ev5_srm__sisr 0 152#define ev5_srm__tbchk 0 153#define ev5_srm__tb1a 0 154#define ev5_srm__tb1ap 0 155#define ev5_srm__tb1ad 0 156#define ev5_srm__tb1ai 0 157#define ev5_srm__tbis 0 158#define ev5_srm__ksp 0 159#define ev5_srm__esp 0 160#define ev5_srm__ssp 0 161#define ev5_srm__usp 0 162#define ev5_srm__vptb 0 163#define ev5_srm__whami 0 164#define ev5_srm__cc 0 165#define ev5_srm__unq 0 166// processor-specific iprs. 167#define ev5__sc_ctl 168 168#define ev5__sc_stat 232 169#define ev5__sc_addr 392 170#define ev5__bc_ctl 296 171#define ev5__bc_config 456 172#define bc_config_k_size_1mb 1 173#define bc_config_k_size_2mb 2 174#define bc_config_k_size_4mb 3 175#define bc_config_k_size_8mb 4 176#define bc_config_k_size_16mb 5 177#define bc_config_k_size_32mb 6 178#define bc_config_k_size_64mb 7 179#define ev5__ei_stat 360 180#define ev5__ei_addr 328 181#define ev5__fill_syn 104 182#define ev5__bc_tag_addr 264 183#define ev5__aster 266 184#define ev5__astrr 265 185#define ev5__exc_addr 267 186#define exc_addr_v_pa 2 187#define exc_addr_s_pa 62 188#define ev5__exc_sum 268 189#define ev5__exc_mask 269 190#define ev5__hwint_clr 277 191#define ev5__ic_flush_ctl 281 192#define ev5__icperr_stat 282 193#define ev5__ic_perr_stat 282 194#define ev5__ic_row_map 283 195#define ev5__icsr 280 196#define ev5__ifault_va_form 274 197#define ev5__ifault_va_form_nt 274 198#define ifault_va_form_nt_v_vptb 30 199#define ifault_va_form_nt_s_vptb 34 200#define ev5__intid 273 201#define ev5__ipl 272 202#define ev5__itb_is 263 203#define ev5__itb_asn 259 204#define ev5__itb_ia 261 205#define ev5__itb_iap 262 206#define ev5__itb_pte 258 207#define ev5__itb_pte_temp 260 208#define ev5__itb_tag 257 209#define ev5__ivptbr 275 210#define ivptbr_v_vptb 30 211#define ivptbr_s_vptb 34 212#define ev5__pal_base 270 213#define ev5__pmctr 284 214#define ev5__ps 271 215#define ev5__isr 256 216#define ev5__sirr 264 217#define ev5__sl_txmit 278 218#define ev5__sl_rcv 279 219#define ev5__alt_mode 524 220#define ev5__cc 525 221#define ev5__cc_ctl 526 222#define ev5__dc_flush 528 223#define ev5__dcperr_stat 530 224#define ev5__dc_test_ctl 531 225#define ev5__dc_test_tag 532 226#define ev5__dc_test_tag_temp 533 227#define ev5__dtb_asn 512 228#define ev5__dtb_cm 513 229#define ev5__dtb_ia 522 230#define ev5__dtb_iap 521 231#define ev5__dtb_is 523 232#define ev5__dtb_pte 515 233#define ev5__dtb_pte_temp 516 234#define ev5__dtb_tag 514 235#define ev5__mcsr 527 236#define ev5__dc_mode 534 237#define ev5__maf_mode 535 238#define ev5__mm_stat 517 239#define ev5__mvptbr 520 240#define ev5__va 518 241#define ev5__va_form 519 242#define ev5__va_form_nt 519 243#define va_form_nt_s_va 19 244#define va_form_nt_v_vptb 30 245#define va_form_nt_s_vptb 34 246#define ev5s_ev5_def 10 247#define ev5_def 0 248// cbox registers. 249#define sc_ctl_v_sc_fhit 0 250#define sc_ctl_v_sc_flush 1 251#define sc_ctl_s_sc_tag_stat 6 252#define sc_ctl_v_sc_tag_stat 2 253#define sc_ctl_s_sc_fb_dp 4 254#define sc_ctl_v_sc_fb_dp 8 255#define sc_ctl_v_sc_blk_size 12 256#define sc_ctl_s_sc_set_en 3 257#define sc_ctl_v_sc_set_en 13 258#define sc_ctl_s_sc_soft_repair 3 259#define sc_ctl_v_sc_soft_repair 16 260#define sc_stat_s_sc_tperr 3 261#define sc_stat_v_sc_tperr 0 262#define sc_stat_s_sc_dperr 8 263#define sc_stat_v_sc_dperr 3 264#define sc_stat_s_cbox_cmd 5 265#define sc_stat_v_cbox_cmd 11 266#define sc_stat_v_sc_scnd_err 16 267#define sc_addr_fhm_v_sc_tag_parity 4 268#define sc_addr_fhm_s_tag_stat_sb0 3 269#define sc_addr_fhm_v_tag_stat_sb0 5 270#define sc_addr_fhm_s_tag_stat_sb1 3 271#define sc_addr_fhm_v_tag_stat_sb1 8 272#define sc_addr_fhm_s_ow_mod0 2 273#define sc_addr_fhm_v_ow_mod0 11 274#define sc_addr_fhm_s_ow_mod1 2 275#define sc_addr_fhm_v_ow_mod1 13 276#define sc_addr_fhm_s_tag_lo 17 277#define sc_addr_fhm_v_tag_lo 15 278#define sc_addr_fhm_s_tag_hi 7 279#define sc_addr_fhm_v_tag_hi 32 280#define bc_ctl_v_bc_enabled 0 281#define bc_ctl_v_alloc_cyc 1 282#define bc_ctl_v_ei_opt_cmd 2 283#define bc_ctl_v_ei_opt_cmd_mb 3 284#define bc_ctl_v_corr_fill_dat 4 285#define bc_ctl_v_vtm_first 5 286#define bc_ctl_v_ei_ecc_or_parity 6 287#define bc_ctl_v_bc_fhit 7 288#define bc_ctl_s_bc_tag_stat 5 289#define bc_ctl_v_bc_tag_stat 8 290#define bc_ctl_s_bc_bad_dat 2 291#define bc_ctl_v_bc_bad_dat 13 292#define bc_ctl_v_ei_dis_err 15 293#define bc_ctl_v_tl_pipe_latch 16 294#define bc_ctl_s_bc_wave_pipe 2 295#define bc_ctl_v_bc_wave_pipe 17 296#define bc_ctl_s_pm_mux_sel 6 297#define bc_ctl_v_pm_mux_sel 19 298#define bc_ctl_v_dbg_mux_sel 25 299#define bc_ctl_v_dis_baf_byp 26 300#define bc_ctl_v_dis_sc_vic_buf 27 301#define bc_ctl_v_dis_sys_addr_par 28 302#define bc_ctl_v_read_dirty_cln_shr 29 303#define bc_ctl_v_write_read_bubble 30 304#define bc_ctl_v_bc_wave_pipe_2 31 305#define bc_ctl_v_auto_dack 32 306#define bc_ctl_v_dis_byte_word 33 307#define bc_ctl_v_stclk_delay 34 308#define bc_ctl_v_write_under_miss 35 309#define bc_config_s_bc_size 3 310#define bc_config_v_bc_size 0 311#define bc_config_s_bc_rd_spd 4 312#define bc_config_v_bc_rd_spd 4 313#define bc_config_s_bc_wr_spd 4 314#define bc_config_v_bc_wr_spd 8 315#define bc_config_s_bc_rd_wr_spc 3 316#define bc_config_v_bc_rd_wr_spc 12 317#define bc_config_s_fill_we_offset 3 318#define bc_config_v_fill_we_offset 16 319#define bc_config_s_bc_we_ctl 9 320#define bc_config_v_bc_we_ctl 20 321// cbox registers, continued 322#define ei_stat_s_sys_id 4 323#define ei_stat_v_sys_id 24 324#define ei_stat_v_bc_tperr 28 325#define ei_stat_v_bc_tc_perr 29 326#define ei_stat_v_ei_es 30 327#define ei_stat_v_cor_ecc_err 31 328#define ei_stat_v_unc_ecc_err 32 329#define ei_stat_v_ei_par_err 33 330#define ei_stat_v_fil_ird 34 331#define ei_stat_v_seo_hrd_err 35 332// 333#define bc_tag_addr_v_hit 12 334#define bc_tag_addr_v_tagctl_p 13 335#define bc_tag_addr_v_tagctl_d 14 336#define bc_tag_addr_v_tagctl_s 15 337#define bc_tag_addr_v_tagctl_v 16 338#define bc_tag_addr_v_tag_p 17 339#define bc_tag_addr_s_bc_tag 19 340#define bc_tag_addr_v_bc_tag 20 341// ibox and icache registers. 342#define aster_v_kar 0 343#define aster_v_ear 1 344#define aster_v_sar 2 345#define aster_v_uar 3 346#define astrr_v_kar 0 347#define astrr_v_ear 1 348#define astrr_v_sar 2 349#define astrr_v_uar 3 350#define exc_addr_v_pal 0 351#define exc_sum_v_swc 10 352#define exc_sum_v_inv 11 353#define exc_sum_v_dze 12 354#define exc_sum_v_fov 13 355#define exc_sum_v_unf 14 356#define exc_sum_v_ine 15 357#define exc_sum_v_iov 16 358#define hwint_clr_v_pc0c 27 359#define hwint_clr_v_pc1c 28 360#define hwint_clr_v_pc2c 29 361#define hwint_clr_v_crdc 32 362#define hwint_clr_v_slc 33 363// ibox and icache registers, continued 364#define icperr_stat_v_dpe 11 365#define icperr_stat_v_tpe 12 366#define icperr_stat_v_tmr 13 367#define ic_perr_stat_v_dpe 11 368#define ic_perr_stat_v_tpe 12 369#define ic_perr_stat_v_tmr 13 370#define icsr_v_pma 8 371#define icsr_v_pmp 9 372#define icsr_v_byt 17 373#define icsr_v_fmp 18 374#define icsr_v_im0 20 375#define icsr_v_im1 21 376#define icsr_v_im2 22 377#define icsr_v_im3 23 378#define icsr_v_tmm 24 379#define icsr_v_tmd 25 380#define icsr_v_fpe 26 381#define icsr_v_hwe 27 382#define icsr_s_spe 2 383#define icsr_v_spe 28 384#define icsr_v_sde 30 385#define icsr_v_crde 32 386#define icsr_v_sle 33 387#define icsr_v_fms 34 388#define icsr_v_fbt 35 389#define icsr_v_fbd 36 390#define icsr_v_dbs 37 391#define icsr_v_ista 38 392#define icsr_v_tst 39 393#define ifault_va_form_s_va 30 394#define ifault_va_form_v_va 3 395#define ifault_va_form_s_vptb 31 396#define ifault_va_form_v_vptb 33 397#define ifault_va_form_nt_s_va 19 398#define ifault_va_form_nt_v_va 3 399#define intid_s_intid 5 400#define intid_v_intid 0 401// ibox and icache registers, continued 402#define ipl_s_ipl 5 403#define ipl_v_ipl 0 404#define itb_is_s_va 30 405#define itb_is_v_va 13 406#define itb_asn_s_asn 7 407#define itb_asn_v_asn 4 408#define itb_pte_v_asm 4 409#define itb_pte_s_gh 2 410#define itb_pte_v_gh 5 411#define itb_pte_v_kre 8 412#define itb_pte_v_ere 9 413#define itb_pte_v_sre 10 414#define itb_pte_v_ure 11 415#define itb_pte_s_pfn 27 416#define itb_pte_v_pfn 32 417#define itb_pte_temp_v_asm 13 418#define itb_pte_temp_v_kre 18 419#define itb_pte_temp_v_ere 19 420#define itb_pte_temp_v_sre 20 421#define itb_pte_temp_v_ure 21 422#define itb_pte_temp_s_gh 3 423#define itb_pte_temp_v_gh 29 424#define itb_pte_temp_s_pfn 27 425#define itb_pte_temp_v_pfn 32 426// ibox and icache registers, continued 427#define itb_tag_s_va 30 428#define itb_tag_v_va 13 429#define pal_base_s_pal_base 26 430#define pal_base_v_pal_base 14 431#define pmctr_s_sel2 4 432#define pmctr_v_sel2 0 433#define pmctr_s_sel1 4 434#define pmctr_v_sel1 4 435#define pmctr_v_killk 8 436#define pmctr_v_killp 9 437#define pmctr_s_ctl2 2 438#define pmctr_v_ctl2 10 439#define pmctr_s_ctl1 2 440#define pmctr_v_ctl1 12 441#define pmctr_s_ctl0 2 442#define pmctr_v_ctl0 14 443#define pmctr_s_ctr2 14 444#define pmctr_v_ctr2 16 445#define pmctr_v_killu 30 446#define pmctr_v_sel0 31 447#define pmctr_s_ctr1 16 448#define pmctr_v_ctr1 32 449#define pmctr_s_ctr0 16 450#define pmctr_v_ctr0 48 451#define ps_v_cm0 3 452#define ps_v_cm1 4 453#define isr_s_astrr 4 454#define isr_v_astrr 0 455#define isr_s_sisr 15 456#define isr_v_sisr 4 457#define isr_v_atr 19 458#define isr_v_i20 20 459#define isr_v_i21 21 460#define isr_v_i22 22 461#define isr_v_i23 23 462#define isr_v_pc0 27 463#define isr_v_pc1 28 464#define isr_v_pc2 29 465#define isr_v_pfl 30 466#define isr_v_mck 31 467#define isr_v_crd 32 468#define isr_v_sli 33 469#define isr_v_hlt 34 470#define sirr_s_sirr 15 471#define sirr_v_sirr 4 472// ibox and icache registers, continued 473#define sl_txmit_v_tmt 7 474#define sl_rcv_v_rcv 6 475// mbox and dcache registers. 476#define alt_mode_v_am0 3 477#define alt_mode_v_am1 4 478#define cc_ctl_v_cc_ena 32 479#define dcperr_stat_v_seo 0 480#define dcperr_stat_v_lock 1 481#define dcperr_stat_v_dp0 2 482#define dcperr_stat_v_dp1 3 483#define dcperr_stat_v_tp0 4 484#define dcperr_stat_v_tp1 5 485// the following two registers are used exclusively for test and diagnostics. 486// they should not be referenced in normal operation. 487#define dc_test_ctl_v_bank0 0 488#define dc_test_ctl_v_bank1 1 489#define dc_test_ctl_v_fill_0 2 490#define dc_test_ctl_s_index 10 491#define dc_test_ctl_v_index 3 492#define dc_test_ctl_s_fill_1 19 493#define dc_test_ctl_v_fill_1 13 494#define dc_test_ctl_s_fill_2 32 495#define dc_test_ctl_v_fill_2 32 496// mbox and dcache registers, continued. 497#define dc_test_tag_v_tag_par 2 498#define dc_test_tag_v_ow0 11 499#define dc_test_tag_v_ow1 12 500#define dc_test_tag_s_tag 26 501#define dc_test_tag_v_tag 13 502#define dc_test_tag_temp_v_tag_par 2 503#define dc_test_tag_temp_v_d0p0 3 504#define dc_test_tag_temp_v_d0p1 4 505#define dc_test_tag_temp_v_d1p0 5 506#define dc_test_tag_temp_v_d1p1 6 507#define dc_test_tag_temp_v_ow0 11 508#define dc_test_tag_temp_v_ow1 12 509#define dc_test_tag_temp_s_tag 26 510#define dc_test_tag_temp_v_tag 13 511#define dtb_asn_s_asn 7 512#define dtb_asn_v_asn 57 513#define dtb_cm_v_cm0 3 514#define dtb_cm_v_cm1 4 515#define dtbis_s_va0 30 516#define dtbis_v_va0 13 517#define dtb_pte_v_for 1 518#define dtb_pte_v_fow 2 519#define dtb_pte_v_asm 4 520#define dtb_pte_s_gh 2 521#define dtb_pte_v_gh 5 522#define dtb_pte_v_kre 8 523#define dtb_pte_v_ere 9 524#define dtb_pte_v_sre 10 525#define dtb_pte_v_ure 11 526#define dtb_pte_v_kwe 12 527#define dtb_pte_v_ewe 13 528#define dtb_pte_v_swe 14 529#define dtb_pte_v_uwe 15 530#define dtb_pte_s_pfn 27 531#define dtb_pte_v_pfn 32 532// mbox and dcache registers, continued. 533#define dtb_pte_temp_v_for 0 534#define dtb_pte_temp_v_fow 1 535#define dtb_pte_temp_v_kre 2 536#define dtb_pte_temp_v_ere 3 537#define dtb_pte_temp_v_sre 4 538#define dtb_pte_temp_v_ure 5 539#define dtb_pte_temp_v_kwe 6 540#define dtb_pte_temp_v_ewe 7 541#define dtb_pte_temp_v_swe 8 542#define dtb_pte_temp_v_uwe 9 543#define dtb_pte_temp_v_asm 10 544#define dtb_pte_temp_s_fill_0 2 545#define dtb_pte_temp_v_fill_0 11 546#define dtb_pte_temp_s_pfn 27 547#define dtb_pte_temp_v_pfn 13 548#define dtb_tag_s_va 30 549#define dtb_tag_v_va 13 550// most mcsr bits are used for testability and diagnostics only. 551// for normal operation, they will be supported in the following configuration: 552// split_dcache = 1, maf_nomerge = 0, wb_flush_always = 0, wb_nomerge = 0, 553// dc_ena<1:0> = 1, dc_fhit = 0, dc_bad_parity = 0 554#define mcsr_v_big_endian 0 555#define mcsr_v_sp0 1 556#define mcsr_v_sp1 2 557#define mcsr_v_mbox_sel 3 558#define mcsr_v_e_big_endian 4 559#define mcsr_v_dbg_packet_sel 5 560#define dc_mode_v_dc_ena 0 561#define dc_mode_v_dc_fhit 1 562#define dc_mode_v_dc_bad_parity 2 563#define dc_mode_v_dc_perr_dis 3 564#define dc_mode_v_dc_doa 4 565#define maf_mode_v_maf_nomerge 0 566#define maf_mode_v_wb_flush_always 1 567#define maf_mode_v_wb_nomerge 2 568#define maf_mode_v_io_nomerge 3 569#define maf_mode_v_wb_cnt_disable 4 570#define maf_mode_v_maf_arb_disable 5 571#define maf_mode_v_dread_pending 6 572#define maf_mode_v_wb_pending 7 573// mbox and dcache registers, continued. 574#define mm_stat_v_wr 0 575#define mm_stat_v_acv 1 576#define mm_stat_v_for 2 577#define mm_stat_v_fow 3 578#define mm_stat_v_dtb_miss 4 579#define mm_stat_v_bad_va 5 580#define mm_stat_s_ra 5 581#define mm_stat_v_ra 6 582#define mm_stat_s_opcode 6 583#define mm_stat_v_opcode 11 584#define mvptbr_s_vptb 31 585#define mvptbr_v_vptb 33 586#define va_form_s_va 30 587#define va_form_v_va 3 588#define va_form_s_vptb 31 589#define va_form_v_vptb 33 590#define va_form_nt_s_va 19 591#define va_form_nt_v_va 3 592//.endm 593 594#endif 595