ev5_defs.h revision 8012
1/* 2Copyright 1995 Hewlett-Packard Development Company, L.P. 3 4Permission is hereby granted, free of charge, to any person obtaining a copy of 5this software and associated documentation files (the "Software"), to deal in 6the Software without restriction, including without limitation the rights to 7use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies 8of the Software, and to permit persons to whom the Software is furnished to do 9so, subject to the following conditions: 10 11The above copyright notice and this permission notice shall be included in all 12copies or substantial portions of the Software. 13 14THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20SOFTWARE. 21*/ 22 23#ifndef EV5_DEFS_INCLUDED 24#define EV5_DEFS_INCLUDED 1 25 26// adapted from the version emailed to lance..pb Nov/95 27 28 29// ******************************************************************************************************************************** 30// Created 25-JUL-1995 14:21:23 by VAX SDL V3.2-12 Source: 21-JUL-1995 11:03:08 EV5$:[EV5.DVT.SUP]EV5_DEFS.SDL;24 31// ******************************************************************************************************************************** 32 33// .MACRO $EV5DEF,..EQU=<=>,..COL=<:> 34// EV5$K_REVISION'..equ'34 35// In the definitions below, registers are annotated with one of the following 36// symbols: 37// 38// RW - The register may be read and written 39// RO - The register may only be read 40// WO - The register may only be written 41// 42// For RO and WO registers, all bits and fields within the register are also 43// read-only or write-only. For RW registers, each bit or field within 44// the register is annotated with one of the following: 45// 46// RW - The bit/field may be read and written 47// RO - The bit/field may be read; writes are ignored 48// WO - The bit/field may be written; reads return an UNPREDICTABLE result. 49// WZ - The bit/field may be written; reads return a 0 50// WC - The bit/field may be read; writes cause state to clear 51// RC - The bit/field may be read, which also causes state to clear; writes are ignored 52// Architecturally-defined (SRM) registers for EVMS 53#define pt0 320 54#define pt1 321 55#define pt2 322 56#define pt3 323 57#define pt4 324 58#define pt5 325 59#define pt6 326 60#define pt7 327 61#define pt8 328 62#define pt9 329 63#define pt10 330 64#define pt11 331 65#define pt12 332 66#define pt13 333 67#define pt14 334 68#define pt15 335 69#define pt16 336 70#define pt17 337 71#define pt18 338 72#define pt19 339 73#define pt20 340 74#define pt21 341 75#define pt22 342 76#define pt23 343 77#define cbox_ipr_offset 16777200 78#define sc_ctl 168 79#define sc_stat 232 80#define sc_addr 392 81#define sc_addr_nm 392 82#define sc_addr_fhm 392 83#define bc_ctl 296 84#define bc_config 456 85#define ei_stat 360 86#define ei_addr 328 87#define fill_syn 104 88#define bc_tag_addr 264 89#define ld_lock 488 90#define aster 266 91#define astrr 265 92#define exc_addr 267 93#define exc_sum 268 94#define exc_mask 269 95#define hwint_clr 277 96#define ic_flush_ctl 281 97#define icperr_stat 282 98#define ic_perr_stat 282 99#define ic_row_map 283 100#define icsr 280 101#define ifault_va_form 274 102#define intid 273 103#define ipl 272 104#define isr 256 105#define itb_is 263 106#define itb_asn 259 107#define itb_ia 261 108#define itb_iap 262 109#define itb_pte 258 110#define itb_pte_temp 260 111#define itb_tag 257 112#define ivptbr 275 113#define pal_base 270 114#define pmctr 284 115// this is not the register ps .. pb #define ps 271 116#define sirr 264 117#define sl_txmit 278 118#define sl_rcv 279 119#define alt_mode 524 120#define cc 525 121#define cc_ctl 526 122#define dc_flush 528 123#define dcperr_stat 530 124#define dc_test_ctl 531 125#define dc_test_tag 532 126#define dc_test_tag_temp 533 127#define dtb_asn 512 128#define dtb_cm 513 129#define dtb_ia 522 130#define dtb_iap 521 131#define dtb_is 523 132#define dtb_pte 515 133#define dtb_pte_temp 516 134#define dtb_tag 514 135#define mcsr 527 136#define dc_mode 534 137#define maf_mode 535 138#define mm_stat 517 139#define mvptbr 520 140#define va 518 141#define va_form 519 142#define ev5_srm__ps 0 143#define ev5_srm__pc 0 144#define ev5_srm__asten 0 145#define ev5_srm__astsr 0 146#define ev5_srm__ipir 0 147#define ev5_srm__ipl 0 148#define ev5_srm__mces 0 149#define ev5_srm__pcbb 0 150#define ev5_srm__prbr 0 151#define ev5_srm__ptbr 0 152#define ev5_srm__scbb 0 153#define ev5_srm__sirr 0 154#define ev5_srm__sisr 0 155#define ev5_srm__tbchk 0 156#define ev5_srm__tb1a 0 157#define ev5_srm__tb1ap 0 158#define ev5_srm__tb1ad 0 159#define ev5_srm__tb1ai 0 160#define ev5_srm__tbis 0 161#define ev5_srm__ksp 0 162#define ev5_srm__esp 0 163#define ev5_srm__ssp 0 164#define ev5_srm__usp 0 165#define ev5_srm__vptb 0 166#define ev5_srm__whami 0 167#define ev5_srm__cc 0 168#define ev5_srm__unq 0 169// processor-specific iprs. 170#define ev5__sc_ctl 168 171#define ev5__sc_stat 232 172#define ev5__sc_addr 392 173#define ev5__bc_ctl 296 174#define ev5__bc_config 456 175#define bc_config_k_size_1mb 1 176#define bc_config_k_size_2mb 2 177#define bc_config_k_size_4mb 3 178#define bc_config_k_size_8mb 4 179#define bc_config_k_size_16mb 5 180#define bc_config_k_size_32mb 6 181#define bc_config_k_size_64mb 7 182#define ev5__ei_stat 360 183#define ev5__ei_addr 328 184#define ev5__fill_syn 104 185#define ev5__bc_tag_addr 264 186#define ev5__aster 266 187#define ev5__astrr 265 188#define ev5__exc_addr 267 189#define exc_addr_v_pa 2 190#define exc_addr_s_pa 62 191#define ev5__exc_sum 268 192#define ev5__exc_mask 269 193#define ev5__hwint_clr 277 194#define ev5__ic_flush_ctl 281 195#define ev5__icperr_stat 282 196#define ev5__ic_perr_stat 282 197#define ev5__ic_row_map 283 198#define ev5__icsr 280 199#define ev5__ifault_va_form 274 200#define ev5__ifault_va_form_nt 274 201#define ifault_va_form_nt_v_vptb 30 202#define ifault_va_form_nt_s_vptb 34 203#define ev5__intid 273 204#define ev5__ipl 272 205#define ev5__itb_is 263 206#define ev5__itb_asn 259 207#define ev5__itb_ia 261 208#define ev5__itb_iap 262 209#define ev5__itb_pte 258 210#define ev5__itb_pte_temp 260 211#define ev5__itb_tag 257 212#define ev5__ivptbr 275 213#define ivptbr_v_vptb 30 214#define ivptbr_s_vptb 34 215#define ev5__pal_base 270 216#define ev5__pmctr 284 217#define ev5__ps 271 218#define ev5__isr 256 219#define ev5__sirr 264 220#define ev5__sl_txmit 278 221#define ev5__sl_rcv 279 222#define ev5__alt_mode 524 223#define ev5__cc 525 224#define ev5__cc_ctl 526 225#define ev5__dc_flush 528 226#define ev5__dcperr_stat 530 227#define ev5__dc_test_ctl 531 228#define ev5__dc_test_tag 532 229#define ev5__dc_test_tag_temp 533 230#define ev5__dtb_asn 512 231#define ev5__dtb_cm 513 232#define ev5__dtb_ia 522 233#define ev5__dtb_iap 521 234#define ev5__dtb_is 523 235#define ev5__dtb_pte 515 236#define ev5__dtb_pte_temp 516 237#define ev5__dtb_tag 514 238#define ev5__mcsr 527 239#define ev5__dc_mode 534 240#define ev5__maf_mode 535 241#define ev5__mm_stat 517 242#define ev5__mvptbr 520 243#define ev5__va 518 244#define ev5__va_form 519 245#define ev5__va_form_nt 519 246#define va_form_nt_s_va 19 247#define va_form_nt_v_vptb 30 248#define va_form_nt_s_vptb 34 249#define ev5s_ev5_def 10 250#define ev5_def 0 251// cbox registers. 252#define sc_ctl_v_sc_fhit 0 253#define sc_ctl_v_sc_flush 1 254#define sc_ctl_s_sc_tag_stat 6 255#define sc_ctl_v_sc_tag_stat 2 256#define sc_ctl_s_sc_fb_dp 4 257#define sc_ctl_v_sc_fb_dp 8 258#define sc_ctl_v_sc_blk_size 12 259#define sc_ctl_s_sc_set_en 3 260#define sc_ctl_v_sc_set_en 13 261#define sc_ctl_s_sc_soft_repair 3 262#define sc_ctl_v_sc_soft_repair 16 263#define sc_stat_s_sc_tperr 3 264#define sc_stat_v_sc_tperr 0 265#define sc_stat_s_sc_dperr 8 266#define sc_stat_v_sc_dperr 3 267#define sc_stat_s_cbox_cmd 5 268#define sc_stat_v_cbox_cmd 11 269#define sc_stat_v_sc_scnd_err 16 270#define sc_addr_fhm_v_sc_tag_parity 4 271#define sc_addr_fhm_s_tag_stat_sb0 3 272#define sc_addr_fhm_v_tag_stat_sb0 5 273#define sc_addr_fhm_s_tag_stat_sb1 3 274#define sc_addr_fhm_v_tag_stat_sb1 8 275#define sc_addr_fhm_s_ow_mod0 2 276#define sc_addr_fhm_v_ow_mod0 11 277#define sc_addr_fhm_s_ow_mod1 2 278#define sc_addr_fhm_v_ow_mod1 13 279#define sc_addr_fhm_s_tag_lo 17 280#define sc_addr_fhm_v_tag_lo 15 281#define sc_addr_fhm_s_tag_hi 7 282#define sc_addr_fhm_v_tag_hi 32 283#define bc_ctl_v_bc_enabled 0 284#define bc_ctl_v_alloc_cyc 1 285#define bc_ctl_v_ei_opt_cmd 2 286#define bc_ctl_v_ei_opt_cmd_mb 3 287#define bc_ctl_v_corr_fill_dat 4 288#define bc_ctl_v_vtm_first 5 289#define bc_ctl_v_ei_ecc_or_parity 6 290#define bc_ctl_v_bc_fhit 7 291#define bc_ctl_s_bc_tag_stat 5 292#define bc_ctl_v_bc_tag_stat 8 293#define bc_ctl_s_bc_bad_dat 2 294#define bc_ctl_v_bc_bad_dat 13 295#define bc_ctl_v_ei_dis_err 15 296#define bc_ctl_v_tl_pipe_latch 16 297#define bc_ctl_s_bc_wave_pipe 2 298#define bc_ctl_v_bc_wave_pipe 17 299#define bc_ctl_s_pm_mux_sel 6 300#define bc_ctl_v_pm_mux_sel 19 301#define bc_ctl_v_dbg_mux_sel 25 302#define bc_ctl_v_dis_baf_byp 26 303#define bc_ctl_v_dis_sc_vic_buf 27 304#define bc_ctl_v_dis_sys_addr_par 28 305#define bc_ctl_v_read_dirty_cln_shr 29 306#define bc_ctl_v_write_read_bubble 30 307#define bc_ctl_v_bc_wave_pipe_2 31 308#define bc_ctl_v_auto_dack 32 309#define bc_ctl_v_dis_byte_word 33 310#define bc_ctl_v_stclk_delay 34 311#define bc_ctl_v_write_under_miss 35 312#define bc_config_s_bc_size 3 313#define bc_config_v_bc_size 0 314#define bc_config_s_bc_rd_spd 4 315#define bc_config_v_bc_rd_spd 4 316#define bc_config_s_bc_wr_spd 4 317#define bc_config_v_bc_wr_spd 8 318#define bc_config_s_bc_rd_wr_spc 3 319#define bc_config_v_bc_rd_wr_spc 12 320#define bc_config_s_fill_we_offset 3 321#define bc_config_v_fill_we_offset 16 322#define bc_config_s_bc_we_ctl 9 323#define bc_config_v_bc_we_ctl 20 324// cbox registers, continued 325#define ei_stat_s_sys_id 4 326#define ei_stat_v_sys_id 24 327#define ei_stat_v_bc_tperr 28 328#define ei_stat_v_bc_tc_perr 29 329#define ei_stat_v_ei_es 30 330#define ei_stat_v_cor_ecc_err 31 331#define ei_stat_v_unc_ecc_err 32 332#define ei_stat_v_ei_par_err 33 333#define ei_stat_v_fil_ird 34 334#define ei_stat_v_seo_hrd_err 35 335// 336#define bc_tag_addr_v_hit 12 337#define bc_tag_addr_v_tagctl_p 13 338#define bc_tag_addr_v_tagctl_d 14 339#define bc_tag_addr_v_tagctl_s 15 340#define bc_tag_addr_v_tagctl_v 16 341#define bc_tag_addr_v_tag_p 17 342#define bc_tag_addr_s_bc_tag 19 343#define bc_tag_addr_v_bc_tag 20 344// ibox and icache registers. 345#define aster_v_kar 0 346#define aster_v_ear 1 347#define aster_v_sar 2 348#define aster_v_uar 3 349#define astrr_v_kar 0 350#define astrr_v_ear 1 351#define astrr_v_sar 2 352#define astrr_v_uar 3 353#define exc_addr_v_pal 0 354#define exc_sum_v_swc 10 355#define exc_sum_v_inv 11 356#define exc_sum_v_dze 12 357#define exc_sum_v_fov 13 358#define exc_sum_v_unf 14 359#define exc_sum_v_ine 15 360#define exc_sum_v_iov 16 361#define hwint_clr_v_pc0c 27 362#define hwint_clr_v_pc1c 28 363#define hwint_clr_v_pc2c 29 364#define hwint_clr_v_crdc 32 365#define hwint_clr_v_slc 33 366// ibox and icache registers, continued 367#define icperr_stat_v_dpe 11 368#define icperr_stat_v_tpe 12 369#define icperr_stat_v_tmr 13 370#define ic_perr_stat_v_dpe 11 371#define ic_perr_stat_v_tpe 12 372#define ic_perr_stat_v_tmr 13 373#define icsr_v_pma 8 374#define icsr_v_pmp 9 375#define icsr_v_byt 17 376#define icsr_v_fmp 18 377#define icsr_v_im0 20 378#define icsr_v_im1 21 379#define icsr_v_im2 22 380#define icsr_v_im3 23 381#define icsr_v_tmm 24 382#define icsr_v_tmd 25 383#define icsr_v_fpe 26 384#define icsr_v_hwe 27 385#define icsr_s_spe 2 386#define icsr_v_spe 28 387#define icsr_v_sde 30 388#define icsr_v_crde 32 389#define icsr_v_sle 33 390#define icsr_v_fms 34 391#define icsr_v_fbt 35 392#define icsr_v_fbd 36 393#define icsr_v_dbs 37 394#define icsr_v_ista 38 395#define icsr_v_tst 39 396#define ifault_va_form_s_va 30 397#define ifault_va_form_v_va 3 398#define ifault_va_form_s_vptb 31 399#define ifault_va_form_v_vptb 33 400#define ifault_va_form_nt_s_va 19 401#define ifault_va_form_nt_v_va 3 402#define intid_s_intid 5 403#define intid_v_intid 0 404// ibox and icache registers, continued 405#define ipl_s_ipl 5 406#define ipl_v_ipl 0 407#define itb_is_s_va 30 408#define itb_is_v_va 13 409#define itb_asn_s_asn 7 410#define itb_asn_v_asn 4 411#define itb_pte_v_asm 4 412#define itb_pte_s_gh 2 413#define itb_pte_v_gh 5 414#define itb_pte_v_kre 8 415#define itb_pte_v_ere 9 416#define itb_pte_v_sre 10 417#define itb_pte_v_ure 11 418#define itb_pte_s_pfn 27 419#define itb_pte_v_pfn 32 420#define itb_pte_temp_v_asm 13 421#define itb_pte_temp_v_kre 18 422#define itb_pte_temp_v_ere 19 423#define itb_pte_temp_v_sre 20 424#define itb_pte_temp_v_ure 21 425#define itb_pte_temp_s_gh 3 426#define itb_pte_temp_v_gh 29 427#define itb_pte_temp_s_pfn 27 428#define itb_pte_temp_v_pfn 32 429// ibox and icache registers, continued 430#define itb_tag_s_va 30 431#define itb_tag_v_va 13 432#define pal_base_s_pal_base 26 433#define pal_base_v_pal_base 14 434#define pmctr_s_sel2 4 435#define pmctr_v_sel2 0 436#define pmctr_s_sel1 4 437#define pmctr_v_sel1 4 438#define pmctr_v_killk 8 439#define pmctr_v_killp 9 440#define pmctr_s_ctl2 2 441#define pmctr_v_ctl2 10 442#define pmctr_s_ctl1 2 443#define pmctr_v_ctl1 12 444#define pmctr_s_ctl0 2 445#define pmctr_v_ctl0 14 446#define pmctr_s_ctr2 14 447#define pmctr_v_ctr2 16 448#define pmctr_v_killu 30 449#define pmctr_v_sel0 31 450#define pmctr_s_ctr1 16 451#define pmctr_v_ctr1 32 452#define pmctr_s_ctr0 16 453#define pmctr_v_ctr0 48 454#define ps_v_cm0 3 455#define ps_v_cm1 4 456#define isr_s_astrr 4 457#define isr_v_astrr 0 458#define isr_s_sisr 15 459#define isr_v_sisr 4 460#define isr_v_atr 19 461#define isr_v_i20 20 462#define isr_v_i21 21 463#define isr_v_i22 22 464#define isr_v_i23 23 465#define isr_v_pc0 27 466#define isr_v_pc1 28 467#define isr_v_pc2 29 468#define isr_v_pfl 30 469#define isr_v_mck 31 470#define isr_v_crd 32 471#define isr_v_sli 33 472#define isr_v_hlt 34 473#define sirr_s_sirr 15 474#define sirr_v_sirr 4 475// ibox and icache registers, continued 476#define sl_txmit_v_tmt 7 477#define sl_rcv_v_rcv 6 478// mbox and dcache registers. 479#define alt_mode_v_am0 3 480#define alt_mode_v_am1 4 481#define cc_ctl_v_cc_ena 32 482#define dcperr_stat_v_seo 0 483#define dcperr_stat_v_lock 1 484#define dcperr_stat_v_dp0 2 485#define dcperr_stat_v_dp1 3 486#define dcperr_stat_v_tp0 4 487#define dcperr_stat_v_tp1 5 488// the following two registers are used exclusively for test and diagnostics. 489// they should not be referenced in normal operation. 490#define dc_test_ctl_v_bank0 0 491#define dc_test_ctl_v_bank1 1 492#define dc_test_ctl_v_fill_0 2 493#define dc_test_ctl_s_index 10 494#define dc_test_ctl_v_index 3 495#define dc_test_ctl_s_fill_1 19 496#define dc_test_ctl_v_fill_1 13 497#define dc_test_ctl_s_fill_2 32 498#define dc_test_ctl_v_fill_2 32 499// mbox and dcache registers, continued. 500#define dc_test_tag_v_tag_par 2 501#define dc_test_tag_v_ow0 11 502#define dc_test_tag_v_ow1 12 503#define dc_test_tag_s_tag 26 504#define dc_test_tag_v_tag 13 505#define dc_test_tag_temp_v_tag_par 2 506#define dc_test_tag_temp_v_d0p0 3 507#define dc_test_tag_temp_v_d0p1 4 508#define dc_test_tag_temp_v_d1p0 5 509#define dc_test_tag_temp_v_d1p1 6 510#define dc_test_tag_temp_v_ow0 11 511#define dc_test_tag_temp_v_ow1 12 512#define dc_test_tag_temp_s_tag 26 513#define dc_test_tag_temp_v_tag 13 514#define dtb_asn_s_asn 7 515#define dtb_asn_v_asn 57 516#define dtb_cm_v_cm0 3 517#define dtb_cm_v_cm1 4 518#define dtbis_s_va0 30 519#define dtbis_v_va0 13 520#define dtb_pte_v_for 1 521#define dtb_pte_v_fow 2 522#define dtb_pte_v_asm 4 523#define dtb_pte_s_gh 2 524#define dtb_pte_v_gh 5 525#define dtb_pte_v_kre 8 526#define dtb_pte_v_ere 9 527#define dtb_pte_v_sre 10 528#define dtb_pte_v_ure 11 529#define dtb_pte_v_kwe 12 530#define dtb_pte_v_ewe 13 531#define dtb_pte_v_swe 14 532#define dtb_pte_v_uwe 15 533#define dtb_pte_s_pfn 27 534#define dtb_pte_v_pfn 32 535// mbox and dcache registers, continued. 536#define dtb_pte_temp_v_for 0 537#define dtb_pte_temp_v_fow 1 538#define dtb_pte_temp_v_kre 2 539#define dtb_pte_temp_v_ere 3 540#define dtb_pte_temp_v_sre 4 541#define dtb_pte_temp_v_ure 5 542#define dtb_pte_temp_v_kwe 6 543#define dtb_pte_temp_v_ewe 7 544#define dtb_pte_temp_v_swe 8 545#define dtb_pte_temp_v_uwe 9 546#define dtb_pte_temp_v_asm 10 547#define dtb_pte_temp_s_fill_0 2 548#define dtb_pte_temp_v_fill_0 11 549#define dtb_pte_temp_s_pfn 27 550#define dtb_pte_temp_v_pfn 13 551#define dtb_tag_s_va 30 552#define dtb_tag_v_va 13 553// most mcsr bits are used for testability and diagnostics only. 554// for normal operation, they will be supported in the following configuration: 555// split_dcache = 1, maf_nomerge = 0, wb_flush_always = 0, wb_nomerge = 0, 556// dc_ena<1:0> = 1, dc_fhit = 0, dc_bad_parity = 0 557#define mcsr_v_big_endian 0 558#define mcsr_v_sp0 1 559#define mcsr_v_sp1 2 560#define mcsr_v_mbox_sel 3 561#define mcsr_v_e_big_endian 4 562#define mcsr_v_dbg_packet_sel 5 563#define dc_mode_v_dc_ena 0 564#define dc_mode_v_dc_fhit 1 565#define dc_mode_v_dc_bad_parity 2 566#define dc_mode_v_dc_perr_dis 3 567#define dc_mode_v_dc_doa 4 568#define maf_mode_v_maf_nomerge 0 569#define maf_mode_v_wb_flush_always 1 570#define maf_mode_v_wb_nomerge 2 571#define maf_mode_v_io_nomerge 3 572#define maf_mode_v_wb_cnt_disable 4 573#define maf_mode_v_maf_arb_disable 5 574#define maf_mode_v_dread_pending 6 575#define maf_mode_v_wb_pending 7 576// mbox and dcache registers, continued. 577#define mm_stat_v_wr 0 578#define mm_stat_v_acv 1 579#define mm_stat_v_for 2 580#define mm_stat_v_fow 3 581#define mm_stat_v_dtb_miss 4 582#define mm_stat_v_bad_va 5 583#define mm_stat_s_ra 5 584#define mm_stat_v_ra 6 585#define mm_stat_s_opcode 6 586#define mm_stat_v_opcode 11 587#define mvptbr_s_vptb 31 588#define mvptbr_v_vptb 33 589#define va_form_s_va 30 590#define va_form_v_va 3 591#define va_form_s_vptb 31 592#define va_form_v_vptb 33 593#define va_form_nt_s_va 19 594#define va_form_nt_v_va 3 595//.endm 596 597#endif 598