ev5_alpha_defs.h revision 7997
1#ifndef EV5_ALPHA_DEFS_INCLUDED 2#define EV5_ALPHA_DEFS_INCLUDED 1 3 4// from ev5_alpha_defs.mar from Lance's fetch directory 5// Lower-caseified and $ signs removed ... pb Nov/95 6 7// .MACRO _ALPHADEFS 8// ALPHADEF_VER == 6 ; Flag the version number of this file. 9// .ENDM 10// .MACRO _PSDEF,_GBL 11// _DEFINI PS,_GBL 12//;+ 13//; PS Layout - PS 14//; Loc Size name function 15//; ------ ------ ______ ----------------------------------- 16//; <31:29> 3 SA stack alignment 17//; <31:13> 24 RES Reserved MBZ 18//; <12:8> 5 IPL Priority level 19//; <7> 1 VMM Virtual Mach Monitor 20//; <6:5> 2 RES Reserved MBZ 21//; <4:3> 2 CM Current Mode 22//; <2> 1 IP Interrupt Pending 23//; <1:0> 2 SW Software bits 24//;- 25 26#define ps_v_sw 0 27#define ps_m_sw (3<<ps_v_sw) 28 29#define ps_v_ip 2 30#define ps_m_ip (1<<ps_v_ip) 31 32#define ps_v_cm 3 33#define ps_m_cm (3<<ps_v_cm) 34 35#define ps_v_vmm 7 36#define ps_m_vmm (1<<ps_v_vmm) 37 38#define ps_v_ipl 8 39#define ps_m_ipl (0x1f<<ps_v_ipl) 40 41#define ps_v_sp (0x38) 42#define ps_m_sp (0x3f<<ps_v_sp) 43 44 45#define ps_c_kern (0x00) 46#define ps_c_exec (0x08) 47#define ps_c_supr (0x10) 48#define ps_c_user (0x18) 49#define ps_c_ipl0 (0x0000) 50#define ps_c_ipl1 (0x0100) 51#define ps_c_ipl2 (0x0200) 52#define ps_c_ipl3 (0x0300) 53#define ps_c_ipl4 (0x0400) 54#define ps_c_ipl5 (0x0500) 55#define ps_c_ipl6 (0x0600) 56#define ps_c_ipl7 (0x0700) 57#define ps_c_ipl8 (0x0800) 58#define ps_c_ipl9 (0x0900) 59#define ps_c_ipl10 (0x0A00) 60#define ps_c_ipl11 (0x0B00) 61#define ps_c_ipl12 (0x0C00) 62#define ps_c_ipl13 (0x0D00) 63#define ps_c_ipl14 (0x0E00) 64#define ps_c_ipl15 (0x0F00) 65#define ps_c_ipl16 (0x1000) 66#define ps_c_ipl17 (0x1100) 67#define ps_c_ipl18 (0x1200) 68#define ps_c_ipl19 (0x1300) 69#define ps_c_ipl20 (0x1400) 70#define ps_c_ipl21 (0x1500) 71#define ps_c_ipl22 (0x1600) 72#define ps_c_ipl23 (0x1700) 73#define ps_c_ipl24 (0x1800) 74#define ps_c_ipl25 (0x1900) 75#define ps_c_ipl26 (0x1A00) 76#define ps_c_ipl27 (0x1B00) 77#define ps_c_ipl28 (0x1C00) 78#define ps_c_ipl29 (0x1D00) 79#define ps_c_ipl30 (0x1E00) 80#define ps_c_ipl31 (0x1F00) 81 82// _DEFEND PS,_GBL,DEF 83// .ENDM 84//;+ 85//; PTE layout - symbol prefix PTE_ 86//; 87//; Loc Size name function 88//; ------ ------ ------ ----------------------------------- 89//; <63:32> 32 PFN Page Frame Number 90//; <31:16> 16 SOFT Bits reserved for software use 91//; <15> 1 UWE User write enable 92//; <14> 1 SWE Super write enable 93//; <13> 1 EWE Exec write enable 94//; <12> 1 KWE Kernel write enable 95//; <11> 1 URE User read enable 96//; <10> 1 SRE Super read enable 97//; <9> 1 ERE Exec read enable 98//; <8> 1 KRE Kernel read enable 99//; <7:6> 2 RES Reserved SBZ 100//; <5> 1 HPF Huge Page Flag 101//; <4> 1 ASM Wild card address space number match 102//; <3> 1 FOE Fault On execute 103//; <2> 1 FOW Fault On Write 104//; <1> 1 FOR Fault On Read 105//; <0> 1 V valid bit 106//;- 107// .MACRO _PTEDEF,_GBL 108// _DEFINI PTE,_GBL 109 110#define pte_v_pfn 32 111#define pte_m_soft (0xFFFF0000) 112#define pte_v_soft 16 113#define pte_m_uwe (0x8000) 114#define pte_v_uwe 15 115#define pte_m_swe (0x4000) 116#define pte_v_swe 14 117#define pte_m_ewe (0x2000) 118#define pte_v_ewe 13 119#define pte_m_kwe (0x1000) 120#define pte_v_kwe 12 121#define pte_m_ure (0x0800) 122#define pte_v_ure 11 123#define pte_m_sre (0x0400) 124#define pte_v_sre 10 125#define pte_m_ere (0x0200) 126#define pte_v_ere 9 127#define pte_m_kre (0x0100) 128#define pte_v_kre 8 129#define pte_m_hpf (0x0020) 130#define pte_v_hpf 5 131#define pte_m_asm (0x0010) 132#define pte_v_asm 4 133#define pte_m_foe (0x0008) 134#define pte_v_foe 3 135#define pte_m_fow (0x0004) 136#define pte_v_fow 2 137#define pte_m_for (0x0002) 138#define pte_v_for 1 139#define pte_m_v (0x0001) 140#define pte_v_v 0 141 142// _DEFEND PTE,_GBL,DEF 143// .ENDM 144//;+ 145//; VA layout - symbol prefix VA_ 146//; 147//; Loc Size name function 148//; ------ ------ ------- ----------------------------------- 149//; <42:33> 10 SEG1 First seg table offset for mapping 150//; <32:23> 10 SEG2 Second seg table offset for mapping 151//; <22:13> 10 SEG3 Third seg table offset for mapping 152//; <12:0> 13 OFFSET Byte within page 153//;- 154// .MACRO _VADEF,_GBL 155// _DEFINI VA,_GBL 156 157#define va_m_offset (0x000000001FFF) 158#define va_v_offset 0 159#define va_m_seg3 (0x0000007FE000) 160#define va_v_seg3 13 161#define va_m_seg2 (0x0001FF800000) 162#define va_v_seg2 23 163#define va_m_seg1 (0x7FE00000000) 164#define va_v_seg1 33 165 166// _DEFEND VA,_GBL,DEF 167// .ENDM 168//;+ 169//; PRIVILEGED CONTEXT BLOCK (PCB) 170//;- 171// .MACRO _PCBDEF,_GBL 172// _DEFINI PCB,_GBL 173#define pcb_q_ksp 0 174#define pcb_q_esp 8 175#define pcb_q_ssp 16 176#define pcb_q_usp 24 177#define pcb_q_ptbr 32 178#define pcb_q_asn 40 179#define pcb_q_ast 48 180#define pcb_q_fen 56 181#define pcb_q_cc 64 182#define pcb_q_unq 72 183#define pcb_q_sct 80 184 185#define pcb_v_asten 0 186#define pcb_m_asten (0x0f<<pcb_v_asten) 187#define pcb_v_astsr 4 188#define pcb_m_astsr (0x0f<<pcb_v_astsr) 189#define pcb_v_dat 63 190#define pcb_v_pme 62 191 192// _DEFEND PCB,_GBL,DEF 193// .ENDM 194//;+ 195//; SYSTEM CONTROL BLOCK (SCB) 196//;- 197// .MACRO _SCBDEF,_GBL 198// _DEFINI SCB,_GBL 199 200#define scb_v_fen (0x0010) 201#define scb_v_acv (0x0080) 202#define scb_v_tnv (0x0090) 203#define scb_v_for (0x00A0) 204#define scb_v_fow (0x00B0) 205#define scb_v_foe (0x00C0) 206#define scb_v_arith (0x0200) 207#define scb_v_kast (0x0240) 208#define scb_v_east (0x0250) 209#define scb_v_sast (0x0260) 210#define scb_v_uast (0x0270) 211#define scb_v_unalign (0x0280) 212#define scb_v_bpt (0x0400) 213#define scb_v_bugchk (0x0410) 214#define scb_v_opcdec (0x0420) 215#define scb_v_illpal (0x0430) 216#define scb_v_trap (0x0440) 217#define scb_v_chmk (0x0480) 218#define scb_v_chme (0x0490) 219#define scb_v_chms (0x04A0) 220#define scb_v_chmu (0x04B0) 221#define scb_v_sw0 (0x0500) 222#define scb_v_sw1 (0x0510) 223#define scb_v_sw2 (0x0520) 224#define scb_v_sw3 (0x0530) 225#define scb_v_sw4 (0x0540) 226#define scb_v_sw5 (0x0550) 227#define scb_v_sw6 (0x0560) 228#define scb_v_sw7 (0x0570) 229#define scb_v_sw8 (0x0580) 230#define scb_v_sw9 (0x0590) 231#define scb_v_sw10 (0x05A0) 232#define scb_v_sw11 (0x05B0) 233#define scb_v_sw12 (0x05C0) 234#define scb_v_sw13 (0x05D0) 235#define scb_v_sw14 (0x05E0) 236#define scb_v_sw15 (0x05F0) 237#define scb_v_clock (0x0600) 238#define scb_v_inter (0x0610) 239#define scb_v_sys_corr_err (0x0620) 240#define scb_v_proc_corr_err (0x0630) 241#define scb_v_pwrfail (0x0640) 242#define scb_v_perfmon (0x0650) 243#define scb_v_sysmchk (0x0660) 244#define scb_v_procmchk (0x0670) 245#define scb_v_passive_rel (0x06F0) 246 247// _DEFEND SCB,_GBL,DEF 248// .ENDM 249//;+ 250//; Stack frame (FRM) 251//;- 252// .MACRO _FRMDEF,_GBL 253// _DEFINI FRM,_GBL 254 255#define frm_v_r2 (0x0000) 256#define frm_v_r3 (0x0008) 257#define frm_v_r4 (0x0010) 258#define frm_v_r5 (0x0018) 259#define frm_v_r6 (0x0020) 260#define frm_v_r7 (0x0028) 261#define frm_v_pc (0x0030) 262#define frm_v_ps (0x0038) 263 264// _DEFEND FRM,_GBL,DEF 265// .ENDM 266//;+ 267//; Exeception summary register (EXS) 268//;- 269// .MACRO _EXSDEF,_GBL 270// _DEFINI EXS,_GBL 271// exs_v_swc <0> ; Software completion 272// exs_v_inv <1> ; Ivalid operation 273// exs_v_dze <2> ; Div by zero 274// exs_v_fov <3> ; Floating point overflow 275// exs_v_unf <4> ; Floating point underflow 276// exs_v_ine <5> ; Floating point inexact 277// exs_v_iov <6> ; Floating convert to integer overflow 278#define exs_v_swc 0 279#define exs_v_inv 1 280#define exs_v_dze 2 281#define exs_v_fov 3 282#define exs_v_unf 4 283#define exs_v_ine 5 284#define exs_v_iov 6 285 286#define exs_m_swc (1<<exs_v_swc) 287#define exs_m_inv (1<<exs_v_inv) 288#define exs_m_dze (1<<exs_v_dze) 289#define exs_m_fov (1<<exs_v_fov) 290#define exs_m_unf (1<<exs_v_unf) 291#define exs_m_ine (1<<exs_v_ine) 292#define exs_m_iov (1<<exs_v_iov) 293 294// _defend exs,_gbl,def 295// .endm 296//;+ 297//; machine check error summary register (mces) 298//;- 299// .macro _mcesdef,_gbl 300// _defini mces,_gbl 301// mces_v_mchk <0> ; machine check in progress 302// mces_v_sce <1> ; system correctable error 303// mces_v_pce <2> ; processor correctable error 304// mces_v_dpc <3> ; disable reporting of processor correctable errors 305// mces_v_dsc <4> ; disable reporting of system correctable errors 306#define mces_v_mchk 0 307#define mces_v_sce 1 308#define mces_v_pce 2 309#define mces_v_dpc 3 310#define mces_v_dsc 4 311 312#define mces_m_mchk (1<<mces_v_mchk) 313#define mces_m_sce (1<<mces_v_sce) 314#define mces_m_pce (1<<mces_v_pce) 315#define mces_m_dpc (1<<mces_v_dpc) 316#define mces_m_dsc (1<<mces_v_dsc) 317#define mces_m_all ((1<<mces_v_mchk) | (1<<mces_v_sce) | (1<<mces_v_pce) | (1<<mces_v_dpc) | (1<<mces_v_dsc)) 318// _defend mces,_gbl,def 319// .endm 320 321 322 323#endif 324