ev5_alpha_defs.h revision 8029
18012Ssaidi@eecs.umich.edu/* 28029Snate@binkert.org * Copyright (c) 1993 The Hewlett-Packard Development Company 38029Snate@binkert.org * All rights reserved. 48013Sbinkertn@umich.edu * 58029Snate@binkert.org * Redistribution and use in source and binary forms, with or without 68029Snate@binkert.org * modification, are permitted provided that the following conditions are 78029Snate@binkert.org * met: redistributions of source code must retain the above copyright 88029Snate@binkert.org * notice, this list of conditions and the following disclaimer; 98029Snate@binkert.org * redistributions in binary form must reproduce the above copyright 108029Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 118029Snate@binkert.org * documentation and/or other materials provided with the distribution; 128029Snate@binkert.org * neither the name of the copyright holders nor the names of its 138029Snate@binkert.org * contributors may be used to endorse or promote products derived from 148029Snate@binkert.org * this software without specific prior written permission. 158013Sbinkertn@umich.edu * 168029Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 178029Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 188029Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 198029Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 208029Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 218029Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 228029Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 238029Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 248029Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 258029Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 268029Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 278013Sbinkertn@umich.edu */ 288012Ssaidi@eecs.umich.edu 297997Ssaidi@eecs.umich.edu#ifndef EV5_ALPHA_DEFS_INCLUDED 307997Ssaidi@eecs.umich.edu#define EV5_ALPHA_DEFS_INCLUDED 1 317997Ssaidi@eecs.umich.edu 327997Ssaidi@eecs.umich.edu// from ev5_alpha_defs.mar from Lance's fetch directory 337997Ssaidi@eecs.umich.edu// Lower-caseified and $ signs removed ... pb Nov/95 347997Ssaidi@eecs.umich.edu 358013Sbinkertn@umich.edu// 368013Sbinkertn@umich.edu// PS Layout - PS 378013Sbinkertn@umich.edu// Loc Size name function 388013Sbinkertn@umich.edu// ------ ------ ______ ----------------------------------- 398013Sbinkertn@umich.edu// <31:29> 3 SA stack alignment 408013Sbinkertn@umich.edu// <31:13> 24 RES Reserved MBZ 418013Sbinkertn@umich.edu// <12:8> 5 IPL Priority level 428013Sbinkertn@umich.edu// <7> 1 VMM Virtual Mach Monitor 438013Sbinkertn@umich.edu// <6:5> 2 RES Reserved MBZ 448013Sbinkertn@umich.edu// <4:3> 2 CM Current Mode 458013Sbinkertn@umich.edu// <2> 1 IP Interrupt Pending 468013Sbinkertn@umich.edu// <1:0> 2 SW Software bits 478013Sbinkertn@umich.edu// 487997Ssaidi@eecs.umich.edu 497997Ssaidi@eecs.umich.edu#define ps_v_sw 0 507997Ssaidi@eecs.umich.edu#define ps_m_sw (3<<ps_v_sw) 517997Ssaidi@eecs.umich.edu 527997Ssaidi@eecs.umich.edu#define ps_v_ip 2 537997Ssaidi@eecs.umich.edu#define ps_m_ip (1<<ps_v_ip) 547997Ssaidi@eecs.umich.edu 557997Ssaidi@eecs.umich.edu#define ps_v_cm 3 567997Ssaidi@eecs.umich.edu#define ps_m_cm (3<<ps_v_cm) 577997Ssaidi@eecs.umich.edu 587997Ssaidi@eecs.umich.edu#define ps_v_vmm 7 597997Ssaidi@eecs.umich.edu#define ps_m_vmm (1<<ps_v_vmm) 607997Ssaidi@eecs.umich.edu 617997Ssaidi@eecs.umich.edu#define ps_v_ipl 8 627997Ssaidi@eecs.umich.edu#define ps_m_ipl (0x1f<<ps_v_ipl) 637997Ssaidi@eecs.umich.edu 647997Ssaidi@eecs.umich.edu#define ps_v_sp (0x38) 657997Ssaidi@eecs.umich.edu#define ps_m_sp (0x3f<<ps_v_sp) 667997Ssaidi@eecs.umich.edu 677997Ssaidi@eecs.umich.edu 687997Ssaidi@eecs.umich.edu#define ps_c_kern (0x00) 697997Ssaidi@eecs.umich.edu#define ps_c_exec (0x08) 707997Ssaidi@eecs.umich.edu#define ps_c_supr (0x10) 717997Ssaidi@eecs.umich.edu#define ps_c_user (0x18) 727997Ssaidi@eecs.umich.edu#define ps_c_ipl0 (0x0000) 737997Ssaidi@eecs.umich.edu#define ps_c_ipl1 (0x0100) 747997Ssaidi@eecs.umich.edu#define ps_c_ipl2 (0x0200) 757997Ssaidi@eecs.umich.edu#define ps_c_ipl3 (0x0300) 767997Ssaidi@eecs.umich.edu#define ps_c_ipl4 (0x0400) 777997Ssaidi@eecs.umich.edu#define ps_c_ipl5 (0x0500) 787997Ssaidi@eecs.umich.edu#define ps_c_ipl6 (0x0600) 797997Ssaidi@eecs.umich.edu#define ps_c_ipl7 (0x0700) 807997Ssaidi@eecs.umich.edu#define ps_c_ipl8 (0x0800) 817997Ssaidi@eecs.umich.edu#define ps_c_ipl9 (0x0900) 827997Ssaidi@eecs.umich.edu#define ps_c_ipl10 (0x0A00) 837997Ssaidi@eecs.umich.edu#define ps_c_ipl11 (0x0B00) 847997Ssaidi@eecs.umich.edu#define ps_c_ipl12 (0x0C00) 857997Ssaidi@eecs.umich.edu#define ps_c_ipl13 (0x0D00) 867997Ssaidi@eecs.umich.edu#define ps_c_ipl14 (0x0E00) 877997Ssaidi@eecs.umich.edu#define ps_c_ipl15 (0x0F00) 887997Ssaidi@eecs.umich.edu#define ps_c_ipl16 (0x1000) 897997Ssaidi@eecs.umich.edu#define ps_c_ipl17 (0x1100) 907997Ssaidi@eecs.umich.edu#define ps_c_ipl18 (0x1200) 917997Ssaidi@eecs.umich.edu#define ps_c_ipl19 (0x1300) 927997Ssaidi@eecs.umich.edu#define ps_c_ipl20 (0x1400) 937997Ssaidi@eecs.umich.edu#define ps_c_ipl21 (0x1500) 947997Ssaidi@eecs.umich.edu#define ps_c_ipl22 (0x1600) 957997Ssaidi@eecs.umich.edu#define ps_c_ipl23 (0x1700) 967997Ssaidi@eecs.umich.edu#define ps_c_ipl24 (0x1800) 977997Ssaidi@eecs.umich.edu#define ps_c_ipl25 (0x1900) 987997Ssaidi@eecs.umich.edu#define ps_c_ipl26 (0x1A00) 997997Ssaidi@eecs.umich.edu#define ps_c_ipl27 (0x1B00) 1007997Ssaidi@eecs.umich.edu#define ps_c_ipl28 (0x1C00) 1017997Ssaidi@eecs.umich.edu#define ps_c_ipl29 (0x1D00) 1027997Ssaidi@eecs.umich.edu#define ps_c_ipl30 (0x1E00) 1037997Ssaidi@eecs.umich.edu#define ps_c_ipl31 (0x1F00) 1047997Ssaidi@eecs.umich.edu 1058013Sbinkertn@umich.edu// 1068013Sbinkertn@umich.edu// PTE layout - symbol prefix PTE_ 1078013Sbinkertn@umich.edu// 1088013Sbinkertn@umich.edu// Loc Size name function 1098013Sbinkertn@umich.edu// ------ ------ ------ ----------------------------------- 1108013Sbinkertn@umich.edu// <63:32> 32 PFN Page Frame Number 1118013Sbinkertn@umich.edu// <31:16> 16 SOFT Bits reserved for software use 1128013Sbinkertn@umich.edu// <15> 1 UWE User write enable 1138013Sbinkertn@umich.edu// <14> 1 SWE Super write enable 1148013Sbinkertn@umich.edu// <13> 1 EWE Exec write enable 1158013Sbinkertn@umich.edu// <12> 1 KWE Kernel write enable 1168013Sbinkertn@umich.edu// <11> 1 URE User read enable 1178013Sbinkertn@umich.edu// <10> 1 SRE Super read enable 1188013Sbinkertn@umich.edu// <9> 1 ERE Exec read enable 1198013Sbinkertn@umich.edu// <8> 1 KRE Kernel read enable 1208013Sbinkertn@umich.edu// <7:6> 2 RES Reserved SBZ 1218013Sbinkertn@umich.edu// <5> 1 HPF Huge Page Flag 1228013Sbinkertn@umich.edu// <4> 1 ASM Wild card address space number match 1238013Sbinkertn@umich.edu// <3> 1 FOE Fault On execute 1248013Sbinkertn@umich.edu// <2> 1 FOW Fault On Write 1258013Sbinkertn@umich.edu// <1> 1 FOR Fault On Read 1268013Sbinkertn@umich.edu// <0> 1 V valid bit 1278013Sbinkertn@umich.edu// 1287997Ssaidi@eecs.umich.edu 1297997Ssaidi@eecs.umich.edu#define pte_v_pfn 32 1307997Ssaidi@eecs.umich.edu#define pte_m_soft (0xFFFF0000) 1317997Ssaidi@eecs.umich.edu#define pte_v_soft 16 1327997Ssaidi@eecs.umich.edu#define pte_m_uwe (0x8000) 1337997Ssaidi@eecs.umich.edu#define pte_v_uwe 15 1347997Ssaidi@eecs.umich.edu#define pte_m_swe (0x4000) 1357997Ssaidi@eecs.umich.edu#define pte_v_swe 14 1367997Ssaidi@eecs.umich.edu#define pte_m_ewe (0x2000) 1377997Ssaidi@eecs.umich.edu#define pte_v_ewe 13 1387997Ssaidi@eecs.umich.edu#define pte_m_kwe (0x1000) 1397997Ssaidi@eecs.umich.edu#define pte_v_kwe 12 1407997Ssaidi@eecs.umich.edu#define pte_m_ure (0x0800) 1417997Ssaidi@eecs.umich.edu#define pte_v_ure 11 1427997Ssaidi@eecs.umich.edu#define pte_m_sre (0x0400) 1437997Ssaidi@eecs.umich.edu#define pte_v_sre 10 1447997Ssaidi@eecs.umich.edu#define pte_m_ere (0x0200) 1457997Ssaidi@eecs.umich.edu#define pte_v_ere 9 1467997Ssaidi@eecs.umich.edu#define pte_m_kre (0x0100) 1477997Ssaidi@eecs.umich.edu#define pte_v_kre 8 1487997Ssaidi@eecs.umich.edu#define pte_m_hpf (0x0020) 1497997Ssaidi@eecs.umich.edu#define pte_v_hpf 5 1507997Ssaidi@eecs.umich.edu#define pte_m_asm (0x0010) 1517997Ssaidi@eecs.umich.edu#define pte_v_asm 4 1527997Ssaidi@eecs.umich.edu#define pte_m_foe (0x0008) 1537997Ssaidi@eecs.umich.edu#define pte_v_foe 3 1547997Ssaidi@eecs.umich.edu#define pte_m_fow (0x0004) 1557997Ssaidi@eecs.umich.edu#define pte_v_fow 2 1567997Ssaidi@eecs.umich.edu#define pte_m_for (0x0002) 1577997Ssaidi@eecs.umich.edu#define pte_v_for 1 1587997Ssaidi@eecs.umich.edu#define pte_m_v (0x0001) 1597997Ssaidi@eecs.umich.edu#define pte_v_v 0 1607997Ssaidi@eecs.umich.edu 1618013Sbinkertn@umich.edu// 1628013Sbinkertn@umich.edu// VA layout - symbol prefix VA_ 1638013Sbinkertn@umich.edu// 1648013Sbinkertn@umich.edu// Loc Size name function 1658013Sbinkertn@umich.edu// ------ ------ ------- ----------------------------------- 1668013Sbinkertn@umich.edu// <42:33> 10 SEG1 First seg table offset for mapping 1678013Sbinkertn@umich.edu// <32:23> 10 SEG2 Second seg table offset for mapping 1688013Sbinkertn@umich.edu// <22:13> 10 SEG3 Third seg table offset for mapping 1698013Sbinkertn@umich.edu// <12:0> 13 OFFSET Byte within page 1708013Sbinkertn@umich.edu// 1717997Ssaidi@eecs.umich.edu 1727997Ssaidi@eecs.umich.edu#define va_m_offset (0x000000001FFF) 1737997Ssaidi@eecs.umich.edu#define va_v_offset 0 1747997Ssaidi@eecs.umich.edu#define va_m_seg3 (0x0000007FE000) 1757997Ssaidi@eecs.umich.edu#define va_v_seg3 13 1767997Ssaidi@eecs.umich.edu#define va_m_seg2 (0x0001FF800000) 1777997Ssaidi@eecs.umich.edu#define va_v_seg2 23 1787997Ssaidi@eecs.umich.edu#define va_m_seg1 (0x7FE00000000) 1797997Ssaidi@eecs.umich.edu#define va_v_seg1 33 1807997Ssaidi@eecs.umich.edu 1818013Sbinkertn@umich.edu// 1828013Sbinkertn@umich.edu//PRIVILEGED CONTEXT BLOCK (PCB) 1838013Sbinkertn@umich.edu// 1847997Ssaidi@eecs.umich.edu#define pcb_q_ksp 0 1857997Ssaidi@eecs.umich.edu#define pcb_q_esp 8 1867997Ssaidi@eecs.umich.edu#define pcb_q_ssp 16 1877997Ssaidi@eecs.umich.edu#define pcb_q_usp 24 1887997Ssaidi@eecs.umich.edu#define pcb_q_ptbr 32 1897997Ssaidi@eecs.umich.edu#define pcb_q_asn 40 1907997Ssaidi@eecs.umich.edu#define pcb_q_ast 48 1917997Ssaidi@eecs.umich.edu#define pcb_q_fen 56 1927997Ssaidi@eecs.umich.edu#define pcb_q_cc 64 1937997Ssaidi@eecs.umich.edu#define pcb_q_unq 72 1947997Ssaidi@eecs.umich.edu#define pcb_q_sct 80 1957997Ssaidi@eecs.umich.edu 1967997Ssaidi@eecs.umich.edu#define pcb_v_asten 0 1977997Ssaidi@eecs.umich.edu#define pcb_m_asten (0x0f<<pcb_v_asten) 1987997Ssaidi@eecs.umich.edu#define pcb_v_astsr 4 1997997Ssaidi@eecs.umich.edu#define pcb_m_astsr (0x0f<<pcb_v_astsr) 2007997Ssaidi@eecs.umich.edu#define pcb_v_dat 63 2017997Ssaidi@eecs.umich.edu#define pcb_v_pme 62 2027997Ssaidi@eecs.umich.edu 2038013Sbinkertn@umich.edu// 2048013Sbinkertn@umich.edu// SYSTEM CONTROL BLOCK (SCB) 2058013Sbinkertn@umich.edu// 2067997Ssaidi@eecs.umich.edu 2077997Ssaidi@eecs.umich.edu#define scb_v_fen (0x0010) 2087997Ssaidi@eecs.umich.edu#define scb_v_acv (0x0080) 2097997Ssaidi@eecs.umich.edu#define scb_v_tnv (0x0090) 2107997Ssaidi@eecs.umich.edu#define scb_v_for (0x00A0) 2117997Ssaidi@eecs.umich.edu#define scb_v_fow (0x00B0) 2127997Ssaidi@eecs.umich.edu#define scb_v_foe (0x00C0) 2137997Ssaidi@eecs.umich.edu#define scb_v_arith (0x0200) 2147997Ssaidi@eecs.umich.edu#define scb_v_kast (0x0240) 2157997Ssaidi@eecs.umich.edu#define scb_v_east (0x0250) 2167997Ssaidi@eecs.umich.edu#define scb_v_sast (0x0260) 2177997Ssaidi@eecs.umich.edu#define scb_v_uast (0x0270) 2187997Ssaidi@eecs.umich.edu#define scb_v_unalign (0x0280) 2197997Ssaidi@eecs.umich.edu#define scb_v_bpt (0x0400) 2207997Ssaidi@eecs.umich.edu#define scb_v_bugchk (0x0410) 2217997Ssaidi@eecs.umich.edu#define scb_v_opcdec (0x0420) 2227997Ssaidi@eecs.umich.edu#define scb_v_illpal (0x0430) 2237997Ssaidi@eecs.umich.edu#define scb_v_trap (0x0440) 2247997Ssaidi@eecs.umich.edu#define scb_v_chmk (0x0480) 2257997Ssaidi@eecs.umich.edu#define scb_v_chme (0x0490) 2267997Ssaidi@eecs.umich.edu#define scb_v_chms (0x04A0) 2277997Ssaidi@eecs.umich.edu#define scb_v_chmu (0x04B0) 2287997Ssaidi@eecs.umich.edu#define scb_v_sw0 (0x0500) 2297997Ssaidi@eecs.umich.edu#define scb_v_sw1 (0x0510) 2307997Ssaidi@eecs.umich.edu#define scb_v_sw2 (0x0520) 2317997Ssaidi@eecs.umich.edu#define scb_v_sw3 (0x0530) 2327997Ssaidi@eecs.umich.edu#define scb_v_sw4 (0x0540) 2337997Ssaidi@eecs.umich.edu#define scb_v_sw5 (0x0550) 2347997Ssaidi@eecs.umich.edu#define scb_v_sw6 (0x0560) 2357997Ssaidi@eecs.umich.edu#define scb_v_sw7 (0x0570) 2367997Ssaidi@eecs.umich.edu#define scb_v_sw8 (0x0580) 2377997Ssaidi@eecs.umich.edu#define scb_v_sw9 (0x0590) 2387997Ssaidi@eecs.umich.edu#define scb_v_sw10 (0x05A0) 2397997Ssaidi@eecs.umich.edu#define scb_v_sw11 (0x05B0) 2407997Ssaidi@eecs.umich.edu#define scb_v_sw12 (0x05C0) 2417997Ssaidi@eecs.umich.edu#define scb_v_sw13 (0x05D0) 2427997Ssaidi@eecs.umich.edu#define scb_v_sw14 (0x05E0) 2437997Ssaidi@eecs.umich.edu#define scb_v_sw15 (0x05F0) 2447997Ssaidi@eecs.umich.edu#define scb_v_clock (0x0600) 2457997Ssaidi@eecs.umich.edu#define scb_v_inter (0x0610) 2467997Ssaidi@eecs.umich.edu#define scb_v_sys_corr_err (0x0620) 2477997Ssaidi@eecs.umich.edu#define scb_v_proc_corr_err (0x0630) 2487997Ssaidi@eecs.umich.edu#define scb_v_pwrfail (0x0640) 2497997Ssaidi@eecs.umich.edu#define scb_v_perfmon (0x0650) 2507997Ssaidi@eecs.umich.edu#define scb_v_sysmchk (0x0660) 2517997Ssaidi@eecs.umich.edu#define scb_v_procmchk (0x0670) 2527997Ssaidi@eecs.umich.edu#define scb_v_passive_rel (0x06F0) 2537997Ssaidi@eecs.umich.edu 2548013Sbinkertn@umich.edu// 2558013Sbinkertn@umich.edu// Stack frame (FRM) 2568013Sbinkertn@umich.edu// 2577997Ssaidi@eecs.umich.edu 2587997Ssaidi@eecs.umich.edu#define frm_v_r2 (0x0000) 2597997Ssaidi@eecs.umich.edu#define frm_v_r3 (0x0008) 2607997Ssaidi@eecs.umich.edu#define frm_v_r4 (0x0010) 2617997Ssaidi@eecs.umich.edu#define frm_v_r5 (0x0018) 2627997Ssaidi@eecs.umich.edu#define frm_v_r6 (0x0020) 2637997Ssaidi@eecs.umich.edu#define frm_v_r7 (0x0028) 2647997Ssaidi@eecs.umich.edu#define frm_v_pc (0x0030) 2657997Ssaidi@eecs.umich.edu#define frm_v_ps (0x0038) 2667997Ssaidi@eecs.umich.edu 2678013Sbinkertn@umich.edu// 2688013Sbinkertn@umich.edu// Exeception summary register (EXS) 2698013Sbinkertn@umich.edu// 2707997Ssaidi@eecs.umich.edu// exs_v_swc <0> ; Software completion 2717997Ssaidi@eecs.umich.edu// exs_v_inv <1> ; Ivalid operation 2727997Ssaidi@eecs.umich.edu// exs_v_dze <2> ; Div by zero 2737997Ssaidi@eecs.umich.edu// exs_v_fov <3> ; Floating point overflow 2747997Ssaidi@eecs.umich.edu// exs_v_unf <4> ; Floating point underflow 2757997Ssaidi@eecs.umich.edu// exs_v_ine <5> ; Floating point inexact 2767997Ssaidi@eecs.umich.edu// exs_v_iov <6> ; Floating convert to integer overflow 2777997Ssaidi@eecs.umich.edu#define exs_v_swc 0 2787997Ssaidi@eecs.umich.edu#define exs_v_inv 1 2797997Ssaidi@eecs.umich.edu#define exs_v_dze 2 2807997Ssaidi@eecs.umich.edu#define exs_v_fov 3 2817997Ssaidi@eecs.umich.edu#define exs_v_unf 4 2827997Ssaidi@eecs.umich.edu#define exs_v_ine 5 2837997Ssaidi@eecs.umich.edu#define exs_v_iov 6 2847997Ssaidi@eecs.umich.edu 2857997Ssaidi@eecs.umich.edu#define exs_m_swc (1<<exs_v_swc) 2867997Ssaidi@eecs.umich.edu#define exs_m_inv (1<<exs_v_inv) 2877997Ssaidi@eecs.umich.edu#define exs_m_dze (1<<exs_v_dze) 2887997Ssaidi@eecs.umich.edu#define exs_m_fov (1<<exs_v_fov) 2897997Ssaidi@eecs.umich.edu#define exs_m_unf (1<<exs_v_unf) 2907997Ssaidi@eecs.umich.edu#define exs_m_ine (1<<exs_v_ine) 2917997Ssaidi@eecs.umich.edu#define exs_m_iov (1<<exs_v_iov) 2927997Ssaidi@eecs.umich.edu 2938013Sbinkertn@umich.edu// 2948013Sbinkertn@umich.edu// machine check error summary register (mces) 2958013Sbinkertn@umich.edu// 2967997Ssaidi@eecs.umich.edu// mces_v_mchk <0> ; machine check in progress 2977997Ssaidi@eecs.umich.edu// mces_v_sce <1> ; system correctable error 2987997Ssaidi@eecs.umich.edu// mces_v_pce <2> ; processor correctable error 2997997Ssaidi@eecs.umich.edu// mces_v_dpc <3> ; disable reporting of processor correctable errors 3007997Ssaidi@eecs.umich.edu// mces_v_dsc <4> ; disable reporting of system correctable errors 3017997Ssaidi@eecs.umich.edu#define mces_v_mchk 0 3027997Ssaidi@eecs.umich.edu#define mces_v_sce 1 3037997Ssaidi@eecs.umich.edu#define mces_v_pce 2 3047997Ssaidi@eecs.umich.edu#define mces_v_dpc 3 3057997Ssaidi@eecs.umich.edu#define mces_v_dsc 4 3067997Ssaidi@eecs.umich.edu 3077997Ssaidi@eecs.umich.edu#define mces_m_mchk (1<<mces_v_mchk) 3087997Ssaidi@eecs.umich.edu#define mces_m_sce (1<<mces_v_sce) 3097997Ssaidi@eecs.umich.edu#define mces_m_pce (1<<mces_v_pce) 3107997Ssaidi@eecs.umich.edu#define mces_m_dpc (1<<mces_v_dpc) 3117997Ssaidi@eecs.umich.edu#define mces_m_dsc (1<<mces_v_dsc) 3127997Ssaidi@eecs.umich.edu#define mces_m_all ((1<<mces_v_mchk) | (1<<mces_v_sce) | (1<<mces_v_pce) | (1<<mces_v_dpc) | (1<<mces_v_dsc)) 3137997Ssaidi@eecs.umich.edu 3147997Ssaidi@eecs.umich.edu#endif 315