dc21164FromGasSources.h revision 8013:2dfcde2e9998
1/* 2 * Copyright 1993 Hewlett-Packard Development Company, L.P. 3 * 4 * Permission is hereby granted, free of charge, to any person 5 * obtaining a copy of this software and associated documentation 6 * files (the "Software"), to deal in the Software without 7 * restriction, including without limitation the rights to use, copy, 8 * modify, merge, publish, distribute, sublicense, and/or sell copies 9 * of the Software, and to permit persons to whom the Software is 10 * furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be 13 * included in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 25#ifndef DC21164FROMGASSOURCES_INCLUDED 26#define DC21164FROMGASSOURCES_INCLUDED 1 27 28/* 29** 30** INTERNAL PROCESSOR REGISTER DEFINITIONS 31** 32** The internal processor register definitions below are annotated 33** with one of the following symbols: 34** 35** RW - The register may be read and written 36** RO - The register may only be read 37** WO - The register may only be written 38** 39** For RO and WO registers, all bits and fields within the register are 40** also read-only or write-only. For RW registers, each bit or field 41** within the register is annotated with one of the following: 42** 43** RW - The bit/field may be read and written 44** RO - The bit/field may be read; writes are ignored 45** WO - The bit/field may be written; reads return UNPREDICTABLE 46** WZ - The bit/field may be written; reads return a zero value 47** W0C - The bit/field may be read; write-zero-to-clear 48** W1C - The bit/field may be read; write-one-to-clear 49** WA - The bit/field may be read; write-anything-to-clear 50** RC - The bit/field may be read, causing state to clear; 51** writes are ignored 52** 53*/ 54 55 56/* 57** 58** Ibox IPR Definitions: 59** 60*/ 61 62// replaced by ev5_defs.h #define isr 0x100 /* RO - Interrupt Summary */ 63#define itbTag 0x101 /* WO - ITB Tag */ 64#define itbPte 0x102 /* RW - ITB Page Table Entry */ 65#define itbAsn 0x103 /* RW - ITB Address Space Number */ 66#define itbPteTemp 0x104 /* RO - ITB Page Table Entry Temporary */ 67#define itbIa 0x105 /* WO - ITB Invalidate All */ 68#define itbIap 0x106 /* WO - ITB Invalidate All Process */ 69#define itbIs 0x107 /* WO - ITB Invalidate Single */ 70// replaced by ev5_defs.h #define sirr 0x108 /* RW - Software Interrupt Request */ 71// replaced by ev5_defs.h #define astrr 0x109 /* RW - Async. System Trap Request */ 72// replaced by ev5_defs.h #define aster 0x10A /* RW - Async. System Trap Enable */ 73#define excAddr 0x10B /* RW - Exception Address */ 74#define excSum 0x10C /* RW - Exception Summary */ 75#define excMask 0x10D /* RO - Exception Mask */ 76#define palBase 0x10E /* RW - PAL Base */ 77#define ips 0x10F /* RW - Processor Status */ 78// replaced by ev5_defs.h #define ipl 0x110 /* RW - Interrupt Priority Level */ 79#define intId 0x111 /* RO - Interrupt ID */ 80#define iFaultVaForm 0x112 /* RO - Formatted Faulting VA */ 81#define iVptBr 0x113 /* RW - I-Stream Virtual Page Table Base */ 82#define hwIntClr 0x115 /* WO - Hardware Interrupt Clear */ 83#define slXmit 0x116 /* WO - Serial Line Transmit */ 84#define slRcv 0x117 /* RO - Serial Line Receive */ 85// replaced by ev5_defs.h #define icsr 0x118 /* RW - Ibox Control/Status */ 86#define icFlush 0x119 /* WO - I-Cache Flush Control */ 87#define flushIc 0x119 /* WO - I-Cache Flush Control (DC21064 Symbol) */ 88#define icPerr 0x11A /* RW - I-Cache Parity Error Status */ 89#define PmCtr 0x11C /* RW - Performance Counter */ 90 91/* 92** 93** Ibox Control/Status Register (ICSR) Bit Summary 94** 95** Extent Size Name Type Function 96** ------ ---- ---- ---- ------------------------------------ 97** <39> 1 TST RW,0 Assert Test Status 98** <38> 1 ISTA RO I-Cache BIST Status 99** <37> 1 DBS RW,1 Debug Port Select 100** <36> 1 FBD RW,0 Force Bad I-Cache Data Parity 101** <35> 1 FBT RW,0 Force Bad I-Cache Tag Parity 102** <34> 1 FMS RW,0 Force I-Cache Miss 103** <33> 1 SLE RW,0 Enable Serial Line Interrupts 104** <32> 1 CRDE RW,0 Enable Correctable Error Interrupts 105** <30> 1 SDE RW,0 Enable PAL Shadow Registers 106** <29:28> 2 SPE RW,0 Enable I-Stream Super Page Mode 107** <27> 1 HWE RW,0 Enable PALRES Instrs in Kernel Mode 108** <26> 1 FPE RW,0 Enable Floating Point Instructions 109** <25> 1 TMD RW,0 Disable Ibox Timeout Counter 110** <24> 1 TMM RW,0 Timeout Counter Mode 111** 112*/ 113 114#define ICSR_V_TST 39 115#define ICSR_M_TST (1<<ICSR_V_TST) 116#define ICSR_V_ISTA 38 117#define ICSR_M_ISTA (1<<ICSR_V_ISTA) 118#define ICSR_V_DBS 37 119#define ICSR_M_DBS (1<<ICSR_V_DBS) 120#define ICSR_V_FBD 36 121#define ICSR_M_FBD (1<<ICSR_V_FBD) 122#define ICSR_V_FBT 35 123#define ICSR_M_FBT (1<<ICSR_V_FBT) 124#define ICSR_V_FMS 34 125#define ICSR_M_FMS (1<<ICSR_V_FMS) 126#define ICSR_V_SLE 33 127#define ICSR_M_SLE (1<<ICSR_V_SLE) 128#define ICSR_V_CRDE 32 129#define ICSR_M_CRDE (1<<ICSR_V_CRDE) 130#define ICSR_V_SDE 30 131#define ICSR_M_SDE (1<<ICSR_V_SDE) 132#define ICSR_V_SPE 28 133#define ICSR_M_SPE (3<<ICSR_V_SPE) 134#define ICSR_V_HWE 27 135#define ICSR_M_HWE (1<<ICSR_V_HWE) 136#define ICSR_V_FPE 26 137#define ICSR_M_FPE (1<<ICSR_V_FPE) 138#define ICSR_V_TMD 25 139#define ICSR_M_TMD (1<<ICSR_V_TMD) 140#define ICSR_V_TMM 24 141#define ICSR_M_TMM (1<<ICSR_V_TMM) 142 143/* 144** 145** Serial Line Tranmit Register (SL_XMIT) 146** 147** Extent Size Name Type Function 148** ------ ---- ---- ---- ------------------------------------ 149** <7> 1 TMT WO,1 Serial line transmit data 150** 151*/ 152 153#define SLXMIT_V_TMT 7 154#define SLXMIT_M_TMT (1<<SLXMIT_V_TMT) 155 156/* 157** 158** Serial Line Receive Register (SL_RCV) 159** 160** Extent Size Name Type Function 161** ------ ---- ---- ---- ------------------------------------ 162** <6> 1 RCV RO Serial line receive data 163** 164*/ 165 166#define SLRCV_V_RCV 6 167#define SLRCV_M_RCV (1<<SLRCV_V_RCV) 168 169/* 170** 171** Icache Parity Error Status Register (ICPERR) Bit Summary 172** 173** Extent Size Name Type Function 174** ------ ---- ---- ---- ------------------------------------ 175** <13> 1 TMR W1C Timeout reset error 176** <12> 1 TPE W1C Tag parity error 177** <11> 1 DPE W1C Data parity error 178** 179*/ 180 181#define ICPERR_V_TMR 13 182#define ICPERR_M_TMR (1<<ICPERR_V_TMR) 183#define ICPERR_V_TPE 12 184#define ICPERR_M_TPE (1<<ICPERR_V_TPE) 185#define ICPERR_V_DPE 11 186#define ICPERR_M_DPE (1<<ICPERR_V_DPE) 187 188#define ICPERR_M_ALL (ICPERR_M_TMR | ICPERR_M_TPE | ICPERR_M_DPE) 189 190/* 191** 192** Exception Summary Register (EXC_SUM) Bit Summary 193** 194** Extent Size Name Type Function 195** ------ ---- ---- ---- ------------------------------------ 196** <16> 1 IOV WA Integer overflow 197** <15> 1 INE WA Inexact result 198** <14> 1 UNF WA Underflow 199** <13> 1 FOV WA Overflow 200** <12> 1 DZE WA Division by zero 201** <11> 1 INV WA Invalid operation 202** <10> 1 SWC WA Software completion 203** 204*/ 205 206#define EXC_V_IOV 16 207#define EXC_M_IOV (1<<EXC_V_IOV) 208#define EXC_V_INE 15 209#define EXC_M_INE (1<<EXC_V_INE) 210#define EXC_V_UNF 14 211#define EXC_M_UNF (1<<EXC_V_UNF) 212#define EXC_V_FOV 13 213#define EXC_M_FOV (1<<EXC_V_FOV) 214#define EXC_V_DZE 12 215#define EXC_M_DZE (1<<EXC_V_DZE) 216#define EXC_V_INV 11 217#define EXC_M_INV (1<<EXC_V_INV) 218#define EXC_V_SWC 10 219#define EXC_M_SWC (1<<EXC_V_SWC) 220 221/* 222** 223** Hardware Interrupt Clear Register (HWINT_CLR) Bit Summary 224** 225** Extent Size Name Type Function 226** ------ ---- ---- ---- --------------------------------- 227** <33> 1 SLC W1C Clear Serial Line interrupt 228** <32> 1 CRDC W1C Clear Correctable Read Data interrupt 229** <29> 1 PC2C W1C Clear Performance Counter 2 interrupt 230** <28> 1 PC1C W1C Clear Performance Counter 1 interrupt 231** <27> 1 PC0C W1C Clear Performance Counter 0 interrupt 232** 233*/ 234 235#define HWINT_V_SLC 33 236#define HWINT_M_SLC (1<<HWINT_V_SLC) 237#define HWINT_V_CRDC 32 238#define HWINT_M_CRDC (1<<HWINT_V_CRDC) 239#define HWINT_V_PC2C 29 240#define HWINT_M_PC2C (1<<HWINT_V_PC2C) 241#define HWINT_V_PC1C 28 242#define HWINT_M_PC1C (1<<HWINT_V_PC1C) 243#define HWINT_V_PC0C 27 244#define HWINT_M_PC0C (1<<HWINT_V_PC0C) 245 246/* 247** 248** Interrupt Summary Register (ISR) Bit Summary 249** 250** Extent Size Name Type Function 251** ------ ---- ---- ---- --------------------------------- 252** <34> 1 HLT RO External Halt interrupt 253** <33> 1 SLI RO Serial Line interrupt 254** <32> 1 CRD RO Correctable ECC errors 255** <31> 1 MCK RO System Machine Check 256** <30> 1 PFL RO Power Fail 257** <29> 1 PC2 RO Performance Counter 2 interrupt 258** <28> 1 PC1 RO Performance Counter 1 interrupt 259** <27> 1 PC0 RO Performance Counter 0 interrupt 260** <23> 1 I23 RO External Hardware interrupt 261** <22> 1 I22 RO External Hardware interrupt 262** <21> 1 I21 RO External Hardware interrupt 263** <20> 1 I20 RO External Hardware interrupt 264** <19> 1 ATR RO Async. System Trap request 265** <18:4> 15 SIRR RO,0 Software Interrupt request 266** <3:0> 4 ASTRR RO Async. System Trap request (USEK) 267** 268**/ 269 270#define ISR_V_HLT 34 271#define ISR_M_HLT (1<<ISR_V_HLT) 272#define ISR_V_SLI 33 273#define ISR_M_SLI (1<<ISR_V_SLI) 274#define ISR_V_CRD 32 275#define ISR_M_CRD (1<<ISR_V_CRD) 276#define ISR_V_MCK 31 277#define ISR_M_MCK (1<<ISR_V_MCK) 278#define ISR_V_PFL 30 279#define ISR_M_PFL (1<<ISR_V_PFL) 280#define ISR_V_PC2 29 281#define ISR_M_PC2 (1<<ISR_V_PC2) 282#define ISR_V_PC1 28 283#define ISR_M_PC1 (1<<ISR_V_PC1) 284#define ISR_V_PC0 27 285#define ISR_M_PC0 (1<<ISR_V_PC0) 286#define ISR_V_I23 23 287#define ISR_M_I23 (1<<ISR_V_I23) 288#define ISR_V_I22 22 289#define ISR_M_I22 (1<<ISR_V_I22) 290#define ISR_V_I21 21 291#define ISR_M_I21 (1<<ISR_V_I21) 292#define ISR_V_I20 20 293#define ISR_M_I20 (1<<ISR_V_I20) 294#define ISR_V_ATR 19 295#define ISR_M_ATR (1<<ISR_V_ATR) 296#define ISR_V_SIRR 4 297#define ISR_M_SIRR (0x7FFF<<ISR_V_SIRR) 298#define ISR_V_ASTRR 0 299#define ISR_M_ASTRR (0xF<<ISR_V_ASTRR) 300 301/* 302** 303** Mbox and D-Cache IPR Definitions: 304** 305*/ 306 307#define dtbAsn 0x200 /* WO - DTB Address Space Number */ 308#define dtbCm 0x201 /* WO - DTB Current Mode */ 309#define dtbTag 0x202 /* WO - DTB Tag */ 310#define dtbPte 0x203 /* RW - DTB Page Table Entry */ 311#define dtbPteTemp 0x204 /* RO - DTB Page Table Entry Temporary */ 312#define mmStat 0x205 /* RO - D-Stream MM Fault Status */ 313// replaced by ev5_defs.h #define va 0x206 /* RO - Faulting Virtual Address */ 314#define vaForm 0x207 /* RO - Formatted Virtual Address */ 315#define mVptBr 0x208 /* WO - Mbox Virtual Page Table Base */ 316#define dtbIap 0x209 /* WO - DTB Invalidate All Process */ 317#define dtbIa 0x20A /* WO - DTB Invalidate All */ 318#define dtbIs 0x20B /* WO - DTB Invalidate Single */ 319#define altMode 0x20C /* WO - Alternate Mode */ 320// replaced by ev5_defs.h #define cc 0x20D /* WO - Cycle Counter */ 321#define ccCtl 0x20E /* WO - Cycle Counter Control */ 322// replaced by ev5_defs.h #define mcsr 0x20F /* RW - Mbox Control Register */ 323#define dcFlush 0x210 /* WO - Dcache Flush */ 324#define dcPerr 0x212 /* RW - Dcache Parity Error Status */ 325#define dcTestCtl 0x213 /* RW - Dcache Test Tag Control */ 326#define dcTestTag 0x214 /* RW - Dcache Test Tag */ 327#define dcTestTagTemp 0x215 /* RW - Dcache Test Tag Temporary */ 328#define dcMode 0x216 /* RW - Dcache Mode */ 329#define mafMode 0x217 /* RW - Miss Address File Mode */ 330 331/* 332** 333** D-Stream MM Fault Status Register (MM_STAT) Bit Summary 334** 335** Extent Size Name Type Function 336** ------ ---- ---- ---- --------------------------------- 337** <16:11> 6 OPCODE RO Opcode of faulting instruction 338** <10:06> 5 RA RO Ra field of faulting instruction 339** <5> 1 BAD_VA RO Bad virtual address 340** <4> 1 DTB_MISS RO Reference resulted in DTB miss 341** <3> 1 FOW RO Fault on write 342** <2> 1 FOR RO Fault on read 343** <1> 1 ACV RO Access violation 344** <0> 1 WR RO Reference type 345** 346*/ 347 348#define MMSTAT_V_OPC 11 349#define MMSTAT_M_OPC (0x3F<<MMSTAT_V_OPC) 350#define MMSTAT_V_RA 6 351#define MMSTAT_M_RA (0x1F<<MMSTAT_V_RA) 352#define MMSTAT_V_BAD_VA 5 353#define MMSTAT_M_BAD_VA (1<<MMSTAT_V_BAD_VA) 354#define MMSTAT_V_DTB_MISS 4 355#define MMSTAT_M_DTB_MISS (1<<MMSTAT_V_DTB_MISS) 356#define MMSTAT_V_FOW 3 357#define MMSTAT_M_FOW (1<<MMSTAT_V_FOW) 358#define MMSTAT_V_FOR 2 359#define MMSTAT_M_FOR (1<<MMSTAT_V_FOR) 360#define MMSTAT_V_ACV 1 361#define MMSTAT_M_ACV (1<<MMSTAT_V_ACV) 362#define MMSTAT_V_WR 0 363#define MMSTAT_M_WR (1<<MMSTAT_V_WR) 364 365 366/* 367** 368** Mbox Control Register (MCSR) Bit Summary 369** 370** Extent Size Name Type Function 371** ------ ---- ---- ---- --------------------------------- 372** <5> 1 DBG1 RW,0 Mbox Debug Packet Select 373** <4> 1 E_BE RW,0 Ebox Big Endian mode enable 374** <3> 1 DBG0 RW,0 Debug Test Select 375** <2:1> 2 SP RW,0 Superpage mode enable 376** <0> 1 M_BE RW,0 Mbox Big Endian mode enable 377** 378*/ 379 380#define MCSR_V_DBG1 5 381#define MCSR_M_DBG1 (1<<MCSR_V_DBG1) 382#define MCSR_V_E_BE 4 383#define MCSR_M_E_BE (1<<MCSR_V_E_BE) 384#define MCSR_V_DBG0 3 385#define MCSR_M_DBG0 (1<<MCSR_V_DBG0) 386#define MCSR_V_SP 1 387#define MCSR_M_SP (3<<MCSR_V_SP) 388#define MCSR_V_M_BE 0 389#define MCSR_M_M_BE (1<<MCSR_V_M_BE) 390 391/* 392** 393** Dcache Parity Error Status Register (DCPERR) Bit Summary 394** 395** Extent Size Name Type Function 396** ------ ---- ---- ---- ------------------------------------ 397** <5> 1 TP1 RO Dcache bank 1 tag parity error 398** <4> 1 TP0 RO Dcache bank 0 tag parity error 399** <3> 1 DP1 RO Dcache bank 1 data parity error 400** <2> 1 DP0 RO Dcache bank 0 data parity error 401** <1> 1 LOCK W1C Locks/clears bits <5:2> 402** <0> 1 SEO W1C Second Dcache parity error occurred 403** 404*/ 405 406#define DCPERR_V_TP1 5 407#define DCPERR_M_TP1 (1<<DCPERR_V_TP1) 408#define DCPERR_V_TP0 4 409#define DCPERR_M_TP0 (1<<DCPERR_V_TP0) 410#define DCPERR_V_DP1 3 411#define DCPERR_M_DP1 (1<<DCPERR_V_DP1) 412#define DCPERR_V_DP0 2 413#define DCPERR_M_DP0 (1<<DCPERR_V_DP0) 414#define DCPERR_V_LOCK 1 415#define DCPERR_M_LOCK (1<<DCPERR_V_LOCK) 416#define DCPERR_V_SEO 0 417#define DCPERR_M_SEO (1<<DCPERR_V_SEO) 418 419#define DCPERR_M_ALL (DCPERR_M_LOCK | DCPERR_M_SEO) 420 421/* 422** 423** Dcache Mode Register (DC_MODE) Bit Summary 424** 425** Extent Size Name Type Function 426** ------ ---- ---- ---- --------------------------------- 427** <4> 1 DOA RO Hardware Dcache Disable 428** <3> 1 PERR_DIS RW,0 Disable Dcache Parity Error reporting 429** <2> 1 BAD_DP RW,0 Force Dcache data bad parity 430** <1> 1 FHIT RW,0 Force Dcache hit 431** <0> 1 ENA RW,0 Software Dcache Enable 432** 433*/ 434 435#define DC_V_DOA 4 436#define DC_M_DOA (1<<DC_V_DOA) 437#define DC_V_PERR_DIS 3 438#define DC_M_PERR_DIS (1<<DC_V_PERR_DIS) 439#define DC_V_BAD_DP 2 440#define DC_M_BAD_DP (1<<DC_V_BAD_DP) 441#define DC_V_FHIT 1 442#define DC_M_FHIT (1<<DC_V_FHIT) 443#define DC_V_ENA 0 444#define DC_M_ENA (1<<DC_V_ENA) 445 446/* 447** 448** Miss Address File Mode Register (MAF_MODE) Bit Summay 449** 450** Extent Size Name Type Function 451** ------ ---- ---- ---- --------------------------------- 452** <7> 1 WB RO,0 If set, pending WB request 453** <6> 1 DREAD RO,0 If set, pending D-read request 454** 455*/ 456 457#define MAF_V_WB_PENDING 7 458#define MAF_M_WB_PENDING (1<<MAF_V_WB_PENDING) 459#define MAF_V_DREAD_PENDING 6 460#define MAF_M_DREAD_PENDING (1<<MAF_V_DREAD_PENDING) 461 462/* 463** 464** Cbox IPR Definitions: 465** 466*/ 467 468#define scCtl 0x0A8 /* RW - Scache Control */ 469#define scStat 0x0E8 /* RO - Scache Error Status */ 470#define scAddr 0x188 /* RO - Scache Error Address */ 471#define bcCtl 0x128 /* WO - Bcache/System Interface Control */ 472#define bcCfg 0x1C8 /* WO - Bcache Configuration Parameters */ 473#define bcTagAddr 0x108 /* RO - Bcache Tag */ 474#define eiStat 0x168 /* RO - Bcache/System Error Status */ 475#define eiAddr 0x148 /* RO - Bcache/System Error Address */ 476#define fillSyn 0x068 /* RO - Fill Syndrome */ 477#define ldLock 0x1E8 /* RO - LDx_L Address */ 478 479/* 480** 481** Scache Control Register (SC_CTL) Bit Summary 482** 483** Extent Size Name Type Function 484** ------ ---- ---- ---- --------------------------------- 485** <15:13> 3 SET_EN RW,1 Set enable 486** <12> 1 BLK_SIZE RW,1 Scache/Bcache block size select 487** <11:08> 4 FB_DP RW,0 Force bad data parity 488** <07:02> 6 TAG_STAT RW Tag status and parity 489** <1> 1 FLUSH RW,0 If set, clear all tag valid bits 490** <0> 1 FHIT RW,0 Force hits 491** 492*/ 493 494#define SC_V_SET_EN 13 495#define SC_M_SET_EN (7<<SC_V_SET_EN) 496#define SC_V_BLK_SIZE 12 497#define SC_M_BLK_SIZE (1<<SC_V_BLK_SIZE) 498#define SC_V_FB_DP 8 499#define SC_M_FB_DP (0xF<<SC_V_FB_DP) 500#define SC_V_TAG_STAT 2 501#define SC_M_TAG_STAT (0x3F<<SC_V_TAG_STAT) 502#define SC_V_FLUSH 1 503#define SC_M_FLUSH (1<<SC_V_FLUSH) 504#define SC_V_FHIT 0 505#define SC_M_FHIT (1<<SC_V_FHIT) 506 507/* 508** 509** Bcache Control Register (BC_CTL) Bit Summary 510** 511** Extent Size Name Type Function 512** ------ ---- ---- ---- --------------------------------- 513** <27> 1 DIS_VIC_BUF WO,0 Disable Scache victim buffer 514** <26> 1 DIS_BAF_BYP WO,0 Disable speculative Bcache reads 515** <25> 1 DBG_MUX_SEL WO,0 Debug MUX select 516** <24:19> 6 PM_MUX_SEL WO,0 Performance counter MUX select 517** <18:17> 2 BC_WAVE WO,0 Number of cycles of wave pipelining 518** <16> 1 TL_PIPE_LATCH WO,0 Pipe system control pins 519** <15> 1 EI_DIS_ERR WO,1 Disable ECC (parity) error 520** <14:13> 2 BC_BAD_DAT WO,0 Force bad data 521** <12:08> 5 BC_TAG_STAT WO Bcache tag status and parity 522** <7> 1 BC_FHIT WO,0 Bcache force hit 523** <6> 1 EI_ECC WO,1 ECC or byte parity mode 524** <5> 1 VTM_FIRST WO,1 Drive out victim block address first 525** <4> 1 CORR_FILL_DAT WO,1 Correct fill data 526** <3> 1 EI_CMD_GRP3 WO,0 Drive MB command to external pins 527** <2> 1 EI_CMD_GRP2 WO,0 Drive LOCK & SET_DIRTY to ext. pins 528** <1> 1 ALLOC_CYC WO,0 Allocate cycle for non-cached LDs. 529** <0> 1 BC_ENA W0,0 Bcache enable 530** 531*/ 532#define BC_V_DIS_SC_VIC_BUF 27 533#define BC_M_DIS_SC_VIC_BUF (1<<BC_V_DIS_SC_VIC_BUF) 534#define BC_V_DIS_BAF_BYP 26 535#define BC_M_DIS_BAF_BYP (1<<BC_V_DIS_BAF_BYP) 536#define BC_V_DBG_MUX_SEL 25 537#define BC_M_DBG_MUX_SEL (1<<BC_V_DBG_MUX_SEL) 538#define BC_V_PM_MUX_SEL 19 539#define BC_M_PM_MUX_SEL (0x3F<<BC_V_PM_MUX_SEL) 540#define BC_V_BC_WAVE 17 541#define BC_M_BC_WAVE (3<<BC_V_BC_WAVE) 542#define BC_V_TL_PIPE_LATCH 16 543#define BC_M_TL_PIPE_LATCH (1<<BC_V_TL_PIPE_LATCH) 544#define BC_V_EI_DIS_ERR 15 545#define BC_M_EI_DIS_ERR (1<<BC_V_EI_DIS_ERR) 546#define BC_V_BC_BAD_DAT 13 547#define BC_M_BC_BAD_DAT (3<<BC_V_BC_BAD_DAT) 548#define BC_V_BC_TAG_STAT 8 549#define BC_M_BC_TAG_STAT (0x1F<<BC_V_BC_TAG_STAT) 550#define BC_V_BC_FHIT 7 551#define BC_M_BC_FHIT (1<<BC_V_BC_FHIT) 552#define BC_V_EI_ECC_OR_PARITY 6 553#define BC_M_EI_ECC_OR_PARITY (1<<BC_V_EI_ECC_OR_PARITY) 554#define BC_V_VTM_FIRST 5 555#define BC_M_VTM_FIRST (1<<BC_V_VTM_FIRST) 556#define BC_V_CORR_FILL_DAT 4 557#define BC_M_CORR_FILL_DAT (1<<BC_V_CORR_FILL_DAT) 558#define BC_V_EI_CMD_GRP3 3 559#define BC_M_EI_CMD_GRP3 (1<<BC_V_EI_CMD_GRP3) 560#define BC_V_EI_CMD_GRP2 2 561#define BC_M_EI_CMD_GRP2 (1<<BC_V_EI_CMD_GRP2) 562#define BC_V_ALLOC_CYC 1 563#define BC_M_ALLOC_CYC (1<<BC_V_ALLOC_CYC) 564#define BC_V_BC_ENA 0 565#define BC_M_BC_ENA (1<<BC_V_BC_ENA) 566 567#define BC_K_DFAULT \ 568 (((BC_M_EI_DIS_ERR) | \ 569 (BC_M_EI_ECC_OR_PARITY) | \ 570 (BC_M_VTM_FIRST) | \ 571 (BC_M_CORR_FILL_DAT))>>1) 572/* 573** 574** Bcache Configuration Register (BC_CONFIG) Bit Summary 575** 576** Extent Size Name Type Function 577** ------ ---- ---- ---- --------------------------------- 578** <35:29> 7 RSVD WO Reserved - Must Be Zero 579** <28:20> 9 WE_CTL WO,0 Bcache write enable control 580** <19:19> 1 RSVD WO,0 Reserved - Must Be Zero 581** <18:16> 3 WE_OFF WO,1 Bcache fill write enable pulse offset 582** <15:15> 1 RSVD WO,0 Reserved - Must Be Zero 583** <14:12> 3 RD_WR_SPC WO,7 Bcache private read/write spacing 584** <11:08> 4 WR_SPD WO,4 Bcache write speed in CPU cycles 585** <07:04> 4 RD_SPD WO,4 Bcache read speed in CPU cycles 586** <03:03> 1 RSVD WO,0 Reserved - Must Be Zero 587** <02:00> 3 SIZE WO,1 Bcache size 588*/ 589#define BC_V_WE_CTL 20 590#define BC_M_WE_CTL (0x1FF<<BC_V_WE_CTL) 591#define BC_V_WE_OFF 16 592#define BC_M_WE_OFF (0x7<<BC_V_WE_OFF) 593#define BC_V_RD_WR_SPC 12 594#define BC_M_RD_WR_SPC (0x7<<BC_V_RD_WR_SPC) 595#define BC_V_WR_SPD 8 596#define BC_M_WR_SPD (0xF<<BC_V_WR_SPD) 597#define BC_V_RD_SPD 4 598#define BC_M_RD_SPD (0xF<<BC_V_RD_SPD) 599#define BC_V_SIZE 0 600#define BC_M_SIZE (0x7<<BC_V_SIZE) 601 602#define BC_K_CONFIG \ 603 ((0x1<<BC_V_WE_OFF) | \ 604 (0x7<<BC_V_RD_WR_SPC) | \ 605 (0x4<<BC_V_WR_SPD) | \ 606 (0x4<<BC_V_RD_SPD) | \ 607 (0x1<<BC_V_SIZE)) 608 609/* 610** 611** DECchip 21164 Privileged Architecture Library Entry Offsets: 612** 613** Entry Name Offset (Hex) 614** 615** RESET 0000 616** IACCVIO 0080 617** INTERRUPT 0100 618** ITB_MISS 0180 619** DTB_MISS (Single) 0200 620** DTB_MISS (Double) 0280 621** UNALIGN 0300 622** D_FAULT 0380 623** MCHK 0400 624** OPCDEC 0480 625** ARITH 0500 626** FEN 0580 627** CALL_PAL (Privileged) 2000 628** CALL_PAL (Unprivileged) 3000 629** 630*/ 631 632#define PAL_RESET_ENTRY 0x0000 633#define PAL_IACCVIO_ENTRY 0x0080 634#define PAL_INTERRUPT_ENTRY 0x0100 635#define PAL_ITB_MISS_ENTRY 0x0180 636#define PAL_DTB_MISS_ENTRY 0x0200 637#define PAL_DOUBLE_MISS_ENTRY 0x0280 638#define PAL_UNALIGN_ENTRY 0x0300 639#define PAL_D_FAULT_ENTRY 0x0380 640#define PAL_MCHK_ENTRY 0x0400 641#define PAL_OPCDEC_ENTRY 0x0480 642#define PAL_ARITH_ENTRY 0x0500 643#define PAL_FEN_ENTRY 0x0580 644#define PAL_CALL_PAL_PRIV_ENTRY 0x2000 645#define PAL_CALL_PAL_UNPRIV_ENTRY 0x3000 646 647/* 648** 649** Architecturally Reserved Opcode (PALRES) Definitions: 650** 651*/ 652 653#define mtpr hw_mtpr 654#define mfpr hw_mfpr 655 656#define ldl_a hw_ldl/a 657#define ldq_a hw_ldq/a 658#define stq_a hw_stq/a 659#define stl_a hw_stl/a 660 661#define ldl_p hw_ldl/p 662#define ldq_p hw_ldq/p 663#define stl_p hw_stl/p 664#define stq_p hw_stq/p 665 666/* 667** Virtual PTE fetch variants of HW_LD. 668*/ 669#define ld_vpte hw_ldq/v 670 671/* 672** Physical mode load-lock and store-conditional variants of 673** HW_LD and HW_ST. 674*/ 675 676#define ldq_lp hw_ldq/pl 677#define stq_cp hw_stq/pc 678 679/* 680** 681** General Purpose Register Definitions: 682** 683*/ 684 685#define r0 $0 686#define r1 $1 687#define r2 $2 688#define r3 $3 689#define r4 $4 690#define r5 $5 691#define r6 $6 692#define r7 $7 693#define r8 $8 694#define r9 $9 695#define r10 $10 696#define r11 $11 697#define r12 $12 698#define r13 $13 699#define r14 $14 700#define r15 $15 701#define r16 $16 702#define r17 $17 703#define r18 $18 704#define r19 $19 705#define r20 $20 706#define r21 $21 707#define r22 $22 708#define r23 $23 709#define r24 $24 710#define r25 $25 711#define r26 $26 712#define r27 $27 713#define r28 $28 714#define r29 $29 715#define r30 $30 716#define r31 $31 717 718/* 719** 720** Floating Point Register Definitions: 721** 722*/ 723 724#define f0 $f0 725#define f1 $f1 726#define f2 $f2 727#define f3 $f3 728#define f4 $f4 729#define f5 $f5 730#define f6 $f6 731#define f7 $f7 732#define f8 $f8 733#define f9 $f9 734#define f10 $f10 735#define f11 $f11 736#define f12 $f12 737#define f13 $f13 738#define f14 $f14 739#define f15 $f15 740#define f16 $f16 741#define f17 $f17 742#define f18 $f18 743#define f19 $f19 744#define f20 $f20 745#define f21 $f21 746#define f22 $f22 747#define f23 $f23 748#define f24 $f24 749#define f25 $f25 750#define f26 $f26 751#define f27 $f27 752#define f28 $f28 753#define f29 $f29 754#define f30 $f30 755#define f31 $f31 756 757/* 758** 759** PAL Temporary Register Definitions: 760** 761*/ 762 763// covered by fetch distribution..pb Nov/95 764 765// #define pt0 0x140 766// #define pt1 0x141 767// #define pt2 0x142 768// #define pt3 0x143 769// #define pt4 0x144 770// #define pt5 0x145 771// #define pt6 0x146 772// #define pt7 0x147 773// #define pt8 0x148 774// #define pt9 0x149 775// #define pt10 0x14A 776// #define pt11 0x14B 777// #define pt12 0x14C 778// #define pt13 0x14D 779// #define pt14 0x14E 780// #define pt15 0x14F 781// #define pt16 0x150 782// #define pt17 0x151 783// #define pt18 0x152 784// #define pt19 0x153 785// #define pt20 0x154 786// #define pt21 0x155 787// #define pt22 0x156 788// #define pt23 0x157 789 790/* 791** PAL Shadow Registers: 792** 793** The DECchip 21164 shadows r8-r14 and r25 when in PALmode and 794** ICSR<SDE> = 1. 795*/ 796 797#define p0 r8 /* ITB/DTB Miss Scratch */ 798#define p1 r9 /* ITB/DTB Miss Scratch */ 799#define p2 r10 /* ITB/DTB Miss Scratch */ 800#define p3 r11 801// #define ps r11 /* Processor Status */ 802#define p4 r12 /* Local Scratch */ 803#define p5 r13 /* Local Scratch */ 804#define p6 r14 /* Local Scratch */ 805#define p7 r25 /* Local Scratch */ 806 807/* 808** SRM Defined State Definitions: 809*/ 810 811/* 812** This table is an accounting of the DECchip 21164 storage used to 813** implement the SRM defined state for OSF/1. 814** 815** IPR Name Internal Storage 816** -------- ---------------- 817** Processor Status ps, dtbCm, ipl, r11 818** Program Counter Ibox 819** Interrupt Entry ptEntInt 820** Arith Trap Entry ptEntArith 821** MM Fault Entry ptEntMM 822** Unaligned Access Entry ptEntUna 823** Instruction Fault Entry ptEntIF 824** Call System Entry ptEntSys 825** User Stack Pointer ptUsp 826** Kernel Stack Pointer ptKsp 827** Kernel Global Pointer ptKgp 828** System Value ptSysVal 829** Page Table Base Register ptPtbr 830** Virtual Page Table Base iVptBr, mVptBr 831** Process Control Block Base ptPcbb 832** Address Space Number itbAsn, dtbAsn 833** Cycle Counter cc, ccCtl 834** Float Point Enable icsr 835** Lock Flag Cbox/System 836** Unique PCB 837** Who-Am-I ptWhami 838*/ 839 840#define ptEntUna pt2 /* Unaligned Access Dispatch Entry */ 841#define ptImpure pt3 /* Pointer To PAL Scratch Area */ 842#define ptEntIF pt7 /* Instruction Fault Dispatch Entry */ 843#define ptIntMask pt8 /* Interrupt Enable Mask */ 844#define ptEntSys pt9 /* Call System Dispatch Entry */ 845#define ptTrap pt11 846#define ptEntInt pt11 /* Hardware Interrupt Dispatch Entry */ 847#define ptEntArith pt12 /* Arithmetic Trap Dispatch Entry */ 848#if defined(KDEBUG) 849#define ptEntDbg pt13 /* Kernel Debugger Dispatch Entry */ 850#endif /* KDEBUG */ 851#define ptMisc pt16 /* Miscellaneous Flags */ 852#define ptWhami pt16 /* Who-Am-I Register Pt16<15:8> */ 853#define ptMces pt16 /* Machine Check Error Summary Pt16<4:0> */ 854#define ptSysVal pt17 /* Per-Processor System Value */ 855#define ptUsp pt18 /* User Stack Pointer */ 856#define ptKsp pt19 /* Kernel Stack Pointer */ 857#define ptPtbr pt20 /* Page Table Base Register */ 858#define ptEntMM pt21 /* MM Fault Dispatch Entry */ 859#define ptKgp pt22 /* Kernel Global Pointer */ 860#define ptPcbb pt23 /* Process Control Block Base */ 861 862/* 863** 864** Miscellaneous PAL State Flags (ptMisc) Bit Summary 865** 866** Extent Size Name Function 867** ------ ---- ---- --------------------------------- 868** <55:48> 8 SWAP Swap PALcode flag -- character 'S' 869** <47:32> 16 MCHK Machine Check Error code 870** <31:16> 16 SCB System Control Block vector 871** <15:08> 8 WHAMI Who-Am-I identifier 872** <04:00> 5 MCES Machine Check Error Summary bits 873** 874*/ 875 876#define PT16_V_MCES 0 877#define PT16_V_WHAMI 8 878#define PT16_V_SCB 16 879#define PT16_V_MCHK 32 880#define PT16_V_SWAP 48 881 882#endif /* DC21164FROMGASSOURCES_INCLUDED */ 883