dc21164FromGasSources.h revision 7997:b91bdbee66c3
1#ifndef DC21164FROMGASSOURCES_INCLUDED 2#define DC21164FROMGASSOURCES_INCLUDED 1 3 4/* 5***************************************************************************** 6** * 7** Copyright � 1993, 1994 * 8** by Digital Equipment Corporation, Maynard, Massachusetts. * 9** * 10** All Rights Reserved * 11** * 12** Permission is hereby granted to use, copy, modify and distribute * 13** this software and its documentation, in both source code and * 14** object code form, and without fee, for the purpose of distribution * 15** of this software or modifications of this software within products * 16** incorporating an integrated circuit implementing Digital's AXP * 17** architecture, regardless of the source of such integrated circuit, * 18** provided that the above copyright notice and this permission notice * 19** appear in all copies, and that the name of Digital Equipment * 20** Corporation not be used in advertising or publicity pertaining to * 21** distribution of the document or software without specific, written * 22** prior permission. * 23** * 24** Digital Equipment Corporation disclaims all warranties and/or * 25** guarantees with regard to this software, including all implied * 26** warranties of fitness for a particular purpose and merchantability, * 27** and makes no representations regarding the use of, or the results * 28** of the use of, the software and documentation in terms of correctness, * 29** accuracy, reliability, currentness or otherwise; and you rely on * 30** the software, documentation and results solely at your own risk. * 31** * 32** AXP is a trademark of Digital Equipment Corporation. * 33** * 34***************************************************************************** 35** 36** FACILITY: 37** 38** DECchip 21164 PALcode 39** 40** MODULE: 41** 42** dc21164.h 43** 44** MODULE DESCRIPTION: 45** 46** DECchip 21164 specific definitions 47** 48** AUTHOR: ER 49** 50** CREATION DATE: 24-Nov-1993 51** 52** $Id: dc21164FromGasSources.h,v 1.1.1.1 1997/10/30 23:27:19 verghese Exp $ 53** 54** MODIFICATION HISTORY: 55** 56** $Log: dc21164FromGasSources.h,v $ 57** Revision 1.1.1.1 1997/10/30 23:27:19 verghese 58** current 10/29/97 59** 60** Revision 1.1 1995/11/18 01:45:46 boyle 61** Initial revision 62** 63** Revision 1.15 1995/04/21 02:06:30 fdh 64** Replaced C++ style comments with Standard C style comments. 65** 66** Revision 1.14 1995/03/20 14:55:23 samberg 67** Add flushIc to make Roger Cruz's life easier. 68** 69** Revision 1.13 1994/12/14 15:52:48 samberg 70** Add slXmit and slRcv bit definitions 71** 72** Revision 1.12 1994/09/07 15:43:49 samberg 73** Changes for Makefile.vpp, take out OSF definition 74** 75** Revision 1.11 1994/07/26 17:38:35 samberg 76** Changes for SD164. 77** 78** Revision 1.10 1994/07/08 17:02:12 samberg 79** Changes to support platform specific additions 80** 81** Revision 1.8 1994/05/31 15:49:21 ericr 82** Moved ptKdebug from pt10 to pt13; pt10 is used in MCHK flows 83** 84** Revision 1.7 1994/05/26 19:29:51 ericr 85** Added BC_CONFIG definitions 86** 87** Revision 1.6 1994/05/25 14:27:25 ericr 88** Added physical bit to ldq_lp and stq_cp macros 89** 90** Revision 1.5 1994/05/20 18:07:50 ericr 91** Changed line comments to C++ style comment character 92** 93** Revision 1.4 1994/01/17 21:46:54 ericr 94** Added floating point register definitions 95** 96** Revision 1.3 1994/01/03 19:31:49 ericr 97** Added cache parity error status register definitions 98** 99** Revision 1.2 1993/12/22 20:42:35 eric 100** Added ptTrap, ptMisc and flag definitions 101** Added PAL shadow regsiter definitions 102** 103** Revision 1.1 1993/12/16 21:55:05 eric 104** Initial revision 105** 106** 107**-- 108*/ 109 110 111/* 112** 113** INTERNAL PROCESSOR REGISTER DEFINITIONS 114** 115** The internal processor register definitions below are annotated 116** with one of the following symbols: 117** 118** RW - The register may be read and written 119** RO - The register may only be read 120** WO - The register may only be written 121** 122** For RO and WO registers, all bits and fields within the register are 123** also read-only or write-only. For RW registers, each bit or field 124** within the register is annotated with one of the following: 125** 126** RW - The bit/field may be read and written 127** RO - The bit/field may be read; writes are ignored 128** WO - The bit/field may be written; reads return UNPREDICTABLE 129** WZ - The bit/field may be written; reads return a zero value 130** W0C - The bit/field may be read; write-zero-to-clear 131** W1C - The bit/field may be read; write-one-to-clear 132** WA - The bit/field may be read; write-anything-to-clear 133** RC - The bit/field may be read, causing state to clear; 134** writes are ignored 135** 136*/ 137 138 139/* 140** 141** Ibox IPR Definitions: 142** 143*/ 144 145// replaced by ev5_defs.h #define isr 0x100 /* RO - Interrupt Summary */ 146#define itbTag 0x101 /* WO - ITB Tag */ 147#define itbPte 0x102 /* RW - ITB Page Table Entry */ 148#define itbAsn 0x103 /* RW - ITB Address Space Number */ 149#define itbPteTemp 0x104 /* RO - ITB Page Table Entry Temporary */ 150#define itbIa 0x105 /* WO - ITB Invalidate All */ 151#define itbIap 0x106 /* WO - ITB Invalidate All Process */ 152#define itbIs 0x107 /* WO - ITB Invalidate Single */ 153// replaced by ev5_defs.h #define sirr 0x108 /* RW - Software Interrupt Request */ 154// replaced by ev5_defs.h #define astrr 0x109 /* RW - Async. System Trap Request */ 155// replaced by ev5_defs.h #define aster 0x10A /* RW - Async. System Trap Enable */ 156#define excAddr 0x10B /* RW - Exception Address */ 157#define excSum 0x10C /* RW - Exception Summary */ 158#define excMask 0x10D /* RO - Exception Mask */ 159#define palBase 0x10E /* RW - PAL Base */ 160#define ips 0x10F /* RW - Processor Status */ 161// replaced by ev5_defs.h #define ipl 0x110 /* RW - Interrupt Priority Level */ 162#define intId 0x111 /* RO - Interrupt ID */ 163#define iFaultVaForm 0x112 /* RO - Formatted Faulting VA */ 164#define iVptBr 0x113 /* RW - I-Stream Virtual Page Table Base */ 165#define hwIntClr 0x115 /* WO - Hardware Interrupt Clear */ 166#define slXmit 0x116 /* WO - Serial Line Transmit */ 167#define slRcv 0x117 /* RO - Serial Line Receive */ 168// replaced by ev5_defs.h #define icsr 0x118 /* RW - Ibox Control/Status */ 169#define icFlush 0x119 /* WO - I-Cache Flush Control */ 170#define flushIc 0x119 /* WO - I-Cache Flush Control (DC21064 Symbol) */ 171#define icPerr 0x11A /* RW - I-Cache Parity Error Status */ 172#define PmCtr 0x11C /* RW - Performance Counter */ 173 174/* 175** 176** Ibox Control/Status Register (ICSR) Bit Summary 177** 178** Extent Size Name Type Function 179** ------ ---- ---- ---- ------------------------------------ 180** <39> 1 TST RW,0 Assert Test Status 181** <38> 1 ISTA RO I-Cache BIST Status 182** <37> 1 DBS RW,1 Debug Port Select 183** <36> 1 FBD RW,0 Force Bad I-Cache Data Parity 184** <35> 1 FBT RW,0 Force Bad I-Cache Tag Parity 185** <34> 1 FMS RW,0 Force I-Cache Miss 186** <33> 1 SLE RW,0 Enable Serial Line Interrupts 187** <32> 1 CRDE RW,0 Enable Correctable Error Interrupts 188** <30> 1 SDE RW,0 Enable PAL Shadow Registers 189** <29:28> 2 SPE RW,0 Enable I-Stream Super Page Mode 190** <27> 1 HWE RW,0 Enable PALRES Instrs in Kernel Mode 191** <26> 1 FPE RW,0 Enable Floating Point Instructions 192** <25> 1 TMD RW,0 Disable Ibox Timeout Counter 193** <24> 1 TMM RW,0 Timeout Counter Mode 194** 195*/ 196 197#define ICSR_V_TST 39 198#define ICSR_M_TST (1<<ICSR_V_TST) 199#define ICSR_V_ISTA 38 200#define ICSR_M_ISTA (1<<ICSR_V_ISTA) 201#define ICSR_V_DBS 37 202#define ICSR_M_DBS (1<<ICSR_V_DBS) 203#define ICSR_V_FBD 36 204#define ICSR_M_FBD (1<<ICSR_V_FBD) 205#define ICSR_V_FBT 35 206#define ICSR_M_FBT (1<<ICSR_V_FBT) 207#define ICSR_V_FMS 34 208#define ICSR_M_FMS (1<<ICSR_V_FMS) 209#define ICSR_V_SLE 33 210#define ICSR_M_SLE (1<<ICSR_V_SLE) 211#define ICSR_V_CRDE 32 212#define ICSR_M_CRDE (1<<ICSR_V_CRDE) 213#define ICSR_V_SDE 30 214#define ICSR_M_SDE (1<<ICSR_V_SDE) 215#define ICSR_V_SPE 28 216#define ICSR_M_SPE (3<<ICSR_V_SPE) 217#define ICSR_V_HWE 27 218#define ICSR_M_HWE (1<<ICSR_V_HWE) 219#define ICSR_V_FPE 26 220#define ICSR_M_FPE (1<<ICSR_V_FPE) 221#define ICSR_V_TMD 25 222#define ICSR_M_TMD (1<<ICSR_V_TMD) 223#define ICSR_V_TMM 24 224#define ICSR_M_TMM (1<<ICSR_V_TMM) 225 226/* 227** 228** Serial Line Tranmit Register (SL_XMIT) 229** 230** Extent Size Name Type Function 231** ------ ---- ---- ---- ------------------------------------ 232** <7> 1 TMT WO,1 Serial line transmit data 233** 234*/ 235 236#define SLXMIT_V_TMT 7 237#define SLXMIT_M_TMT (1<<SLXMIT_V_TMT) 238 239/* 240** 241** Serial Line Receive Register (SL_RCV) 242** 243** Extent Size Name Type Function 244** ------ ---- ---- ---- ------------------------------------ 245** <6> 1 RCV RO Serial line receive data 246** 247*/ 248 249#define SLRCV_V_RCV 6 250#define SLRCV_M_RCV (1<<SLRCV_V_RCV) 251 252/* 253** 254** Icache Parity Error Status Register (ICPERR) Bit Summary 255** 256** Extent Size Name Type Function 257** ------ ---- ---- ---- ------------------------------------ 258** <13> 1 TMR W1C Timeout reset error 259** <12> 1 TPE W1C Tag parity error 260** <11> 1 DPE W1C Data parity error 261** 262*/ 263 264#define ICPERR_V_TMR 13 265#define ICPERR_M_TMR (1<<ICPERR_V_TMR) 266#define ICPERR_V_TPE 12 267#define ICPERR_M_TPE (1<<ICPERR_V_TPE) 268#define ICPERR_V_DPE 11 269#define ICPERR_M_DPE (1<<ICPERR_V_DPE) 270 271#define ICPERR_M_ALL (ICPERR_M_TMR | ICPERR_M_TPE | ICPERR_M_DPE) 272 273/* 274** 275** Exception Summary Register (EXC_SUM) Bit Summary 276** 277** Extent Size Name Type Function 278** ------ ---- ---- ---- ------------------------------------ 279** <16> 1 IOV WA Integer overflow 280** <15> 1 INE WA Inexact result 281** <14> 1 UNF WA Underflow 282** <13> 1 FOV WA Overflow 283** <12> 1 DZE WA Division by zero 284** <11> 1 INV WA Invalid operation 285** <10> 1 SWC WA Software completion 286** 287*/ 288 289#define EXC_V_IOV 16 290#define EXC_M_IOV (1<<EXC_V_IOV) 291#define EXC_V_INE 15 292#define EXC_M_INE (1<<EXC_V_INE) 293#define EXC_V_UNF 14 294#define EXC_M_UNF (1<<EXC_V_UNF) 295#define EXC_V_FOV 13 296#define EXC_M_FOV (1<<EXC_V_FOV) 297#define EXC_V_DZE 12 298#define EXC_M_DZE (1<<EXC_V_DZE) 299#define EXC_V_INV 11 300#define EXC_M_INV (1<<EXC_V_INV) 301#define EXC_V_SWC 10 302#define EXC_M_SWC (1<<EXC_V_SWC) 303 304/* 305** 306** Hardware Interrupt Clear Register (HWINT_CLR) Bit Summary 307** 308** Extent Size Name Type Function 309** ------ ---- ---- ---- --------------------------------- 310** <33> 1 SLC W1C Clear Serial Line interrupt 311** <32> 1 CRDC W1C Clear Correctable Read Data interrupt 312** <29> 1 PC2C W1C Clear Performance Counter 2 interrupt 313** <28> 1 PC1C W1C Clear Performance Counter 1 interrupt 314** <27> 1 PC0C W1C Clear Performance Counter 0 interrupt 315** 316*/ 317 318#define HWINT_V_SLC 33 319#define HWINT_M_SLC (1<<HWINT_V_SLC) 320#define HWINT_V_CRDC 32 321#define HWINT_M_CRDC (1<<HWINT_V_CRDC) 322#define HWINT_V_PC2C 29 323#define HWINT_M_PC2C (1<<HWINT_V_PC2C) 324#define HWINT_V_PC1C 28 325#define HWINT_M_PC1C (1<<HWINT_V_PC1C) 326#define HWINT_V_PC0C 27 327#define HWINT_M_PC0C (1<<HWINT_V_PC0C) 328 329/* 330** 331** Interrupt Summary Register (ISR) Bit Summary 332** 333** Extent Size Name Type Function 334** ------ ---- ---- ---- --------------------------------- 335** <34> 1 HLT RO External Halt interrupt 336** <33> 1 SLI RO Serial Line interrupt 337** <32> 1 CRD RO Correctable ECC errors 338** <31> 1 MCK RO System Machine Check 339** <30> 1 PFL RO Power Fail 340** <29> 1 PC2 RO Performance Counter 2 interrupt 341** <28> 1 PC1 RO Performance Counter 1 interrupt 342** <27> 1 PC0 RO Performance Counter 0 interrupt 343** <23> 1 I23 RO External Hardware interrupt 344** <22> 1 I22 RO External Hardware interrupt 345** <21> 1 I21 RO External Hardware interrupt 346** <20> 1 I20 RO External Hardware interrupt 347** <19> 1 ATR RO Async. System Trap request 348** <18:4> 15 SIRR RO,0 Software Interrupt request 349** <3:0> 4 ASTRR RO Async. System Trap request (USEK) 350** 351**/ 352 353#define ISR_V_HLT 34 354#define ISR_M_HLT (1<<ISR_V_HLT) 355#define ISR_V_SLI 33 356#define ISR_M_SLI (1<<ISR_V_SLI) 357#define ISR_V_CRD 32 358#define ISR_M_CRD (1<<ISR_V_CRD) 359#define ISR_V_MCK 31 360#define ISR_M_MCK (1<<ISR_V_MCK) 361#define ISR_V_PFL 30 362#define ISR_M_PFL (1<<ISR_V_PFL) 363#define ISR_V_PC2 29 364#define ISR_M_PC2 (1<<ISR_V_PC2) 365#define ISR_V_PC1 28 366#define ISR_M_PC1 (1<<ISR_V_PC1) 367#define ISR_V_PC0 27 368#define ISR_M_PC0 (1<<ISR_V_PC0) 369#define ISR_V_I23 23 370#define ISR_M_I23 (1<<ISR_V_I23) 371#define ISR_V_I22 22 372#define ISR_M_I22 (1<<ISR_V_I22) 373#define ISR_V_I21 21 374#define ISR_M_I21 (1<<ISR_V_I21) 375#define ISR_V_I20 20 376#define ISR_M_I20 (1<<ISR_V_I20) 377#define ISR_V_ATR 19 378#define ISR_M_ATR (1<<ISR_V_ATR) 379#define ISR_V_SIRR 4 380#define ISR_M_SIRR (0x7FFF<<ISR_V_SIRR) 381#define ISR_V_ASTRR 0 382#define ISR_M_ASTRR (0xF<<ISR_V_ASTRR) 383 384/* 385** 386** Mbox and D-Cache IPR Definitions: 387** 388*/ 389 390#define dtbAsn 0x200 /* WO - DTB Address Space Number */ 391#define dtbCm 0x201 /* WO - DTB Current Mode */ 392#define dtbTag 0x202 /* WO - DTB Tag */ 393#define dtbPte 0x203 /* RW - DTB Page Table Entry */ 394#define dtbPteTemp 0x204 /* RO - DTB Page Table Entry Temporary */ 395#define mmStat 0x205 /* RO - D-Stream MM Fault Status */ 396// replaced by ev5_defs.h #define va 0x206 /* RO - Faulting Virtual Address */ 397#define vaForm 0x207 /* RO - Formatted Virtual Address */ 398#define mVptBr 0x208 /* WO - Mbox Virtual Page Table Base */ 399#define dtbIap 0x209 /* WO - DTB Invalidate All Process */ 400#define dtbIa 0x20A /* WO - DTB Invalidate All */ 401#define dtbIs 0x20B /* WO - DTB Invalidate Single */ 402#define altMode 0x20C /* WO - Alternate Mode */ 403// replaced by ev5_defs.h #define cc 0x20D /* WO - Cycle Counter */ 404#define ccCtl 0x20E /* WO - Cycle Counter Control */ 405// replaced by ev5_defs.h #define mcsr 0x20F /* RW - Mbox Control Register */ 406#define dcFlush 0x210 /* WO - Dcache Flush */ 407#define dcPerr 0x212 /* RW - Dcache Parity Error Status */ 408#define dcTestCtl 0x213 /* RW - Dcache Test Tag Control */ 409#define dcTestTag 0x214 /* RW - Dcache Test Tag */ 410#define dcTestTagTemp 0x215 /* RW - Dcache Test Tag Temporary */ 411#define dcMode 0x216 /* RW - Dcache Mode */ 412#define mafMode 0x217 /* RW - Miss Address File Mode */ 413 414/* 415** 416** D-Stream MM Fault Status Register (MM_STAT) Bit Summary 417** 418** Extent Size Name Type Function 419** ------ ---- ---- ---- --------------------------------- 420** <16:11> 6 OPCODE RO Opcode of faulting instruction 421** <10:06> 5 RA RO Ra field of faulting instruction 422** <5> 1 BAD_VA RO Bad virtual address 423** <4> 1 DTB_MISS RO Reference resulted in DTB miss 424** <3> 1 FOW RO Fault on write 425** <2> 1 FOR RO Fault on read 426** <1> 1 ACV RO Access violation 427** <0> 1 WR RO Reference type 428** 429*/ 430 431#define MMSTAT_V_OPC 11 432#define MMSTAT_M_OPC (0x3F<<MMSTAT_V_OPC) 433#define MMSTAT_V_RA 6 434#define MMSTAT_M_RA (0x1F<<MMSTAT_V_RA) 435#define MMSTAT_V_BAD_VA 5 436#define MMSTAT_M_BAD_VA (1<<MMSTAT_V_BAD_VA) 437#define MMSTAT_V_DTB_MISS 4 438#define MMSTAT_M_DTB_MISS (1<<MMSTAT_V_DTB_MISS) 439#define MMSTAT_V_FOW 3 440#define MMSTAT_M_FOW (1<<MMSTAT_V_FOW) 441#define MMSTAT_V_FOR 2 442#define MMSTAT_M_FOR (1<<MMSTAT_V_FOR) 443#define MMSTAT_V_ACV 1 444#define MMSTAT_M_ACV (1<<MMSTAT_V_ACV) 445#define MMSTAT_V_WR 0 446#define MMSTAT_M_WR (1<<MMSTAT_V_WR) 447 448 449/* 450** 451** Mbox Control Register (MCSR) Bit Summary 452** 453** Extent Size Name Type Function 454** ------ ---- ---- ---- --------------------------------- 455** <5> 1 DBG1 RW,0 Mbox Debug Packet Select 456** <4> 1 E_BE RW,0 Ebox Big Endian mode enable 457** <3> 1 DBG0 RW,0 Debug Test Select 458** <2:1> 2 SP RW,0 Superpage mode enable 459** <0> 1 M_BE RW,0 Mbox Big Endian mode enable 460** 461*/ 462 463#define MCSR_V_DBG1 5 464#define MCSR_M_DBG1 (1<<MCSR_V_DBG1) 465#define MCSR_V_E_BE 4 466#define MCSR_M_E_BE (1<<MCSR_V_E_BE) 467#define MCSR_V_DBG0 3 468#define MCSR_M_DBG0 (1<<MCSR_V_DBG0) 469#define MCSR_V_SP 1 470#define MCSR_M_SP (3<<MCSR_V_SP) 471#define MCSR_V_M_BE 0 472#define MCSR_M_M_BE (1<<MCSR_V_M_BE) 473 474/* 475** 476** Dcache Parity Error Status Register (DCPERR) Bit Summary 477** 478** Extent Size Name Type Function 479** ------ ---- ---- ---- ------------------------------------ 480** <5> 1 TP1 RO Dcache bank 1 tag parity error 481** <4> 1 TP0 RO Dcache bank 0 tag parity error 482** <3> 1 DP1 RO Dcache bank 1 data parity error 483** <2> 1 DP0 RO Dcache bank 0 data parity error 484** <1> 1 LOCK W1C Locks/clears bits <5:2> 485** <0> 1 SEO W1C Second Dcache parity error occurred 486** 487*/ 488 489#define DCPERR_V_TP1 5 490#define DCPERR_M_TP1 (1<<DCPERR_V_TP1) 491#define DCPERR_V_TP0 4 492#define DCPERR_M_TP0 (1<<DCPERR_V_TP0) 493#define DCPERR_V_DP1 3 494#define DCPERR_M_DP1 (1<<DCPERR_V_DP1) 495#define DCPERR_V_DP0 2 496#define DCPERR_M_DP0 (1<<DCPERR_V_DP0) 497#define DCPERR_V_LOCK 1 498#define DCPERR_M_LOCK (1<<DCPERR_V_LOCK) 499#define DCPERR_V_SEO 0 500#define DCPERR_M_SEO (1<<DCPERR_V_SEO) 501 502#define DCPERR_M_ALL (DCPERR_M_LOCK | DCPERR_M_SEO) 503 504/* 505** 506** Dcache Mode Register (DC_MODE) Bit Summary 507** 508** Extent Size Name Type Function 509** ------ ---- ---- ---- --------------------------------- 510** <4> 1 DOA RO Hardware Dcache Disable 511** <3> 1 PERR_DIS RW,0 Disable Dcache Parity Error reporting 512** <2> 1 BAD_DP RW,0 Force Dcache data bad parity 513** <1> 1 FHIT RW,0 Force Dcache hit 514** <0> 1 ENA RW,0 Software Dcache Enable 515** 516*/ 517 518#define DC_V_DOA 4 519#define DC_M_DOA (1<<DC_V_DOA) 520#define DC_V_PERR_DIS 3 521#define DC_M_PERR_DIS (1<<DC_V_PERR_DIS) 522#define DC_V_BAD_DP 2 523#define DC_M_BAD_DP (1<<DC_V_BAD_DP) 524#define DC_V_FHIT 1 525#define DC_M_FHIT (1<<DC_V_FHIT) 526#define DC_V_ENA 0 527#define DC_M_ENA (1<<DC_V_ENA) 528 529/* 530** 531** Miss Address File Mode Register (MAF_MODE) Bit Summay 532** 533** Extent Size Name Type Function 534** ------ ---- ---- ---- --------------------------------- 535** <7> 1 WB RO,0 If set, pending WB request 536** <6> 1 DREAD RO,0 If set, pending D-read request 537** 538*/ 539 540#define MAF_V_WB_PENDING 7 541#define MAF_M_WB_PENDING (1<<MAF_V_WB_PENDING) 542#define MAF_V_DREAD_PENDING 6 543#define MAF_M_DREAD_PENDING (1<<MAF_V_DREAD_PENDING) 544 545/* 546** 547** Cbox IPR Definitions: 548** 549*/ 550 551#define scCtl 0x0A8 /* RW - Scache Control */ 552#define scStat 0x0E8 /* RO - Scache Error Status */ 553#define scAddr 0x188 /* RO - Scache Error Address */ 554#define bcCtl 0x128 /* WO - Bcache/System Interface Control */ 555#define bcCfg 0x1C8 /* WO - Bcache Configuration Parameters */ 556#define bcTagAddr 0x108 /* RO - Bcache Tag */ 557#define eiStat 0x168 /* RO - Bcache/System Error Status */ 558#define eiAddr 0x148 /* RO - Bcache/System Error Address */ 559#define fillSyn 0x068 /* RO - Fill Syndrome */ 560#define ldLock 0x1E8 /* RO - LDx_L Address */ 561 562/* 563** 564** Scache Control Register (SC_CTL) Bit Summary 565** 566** Extent Size Name Type Function 567** ------ ---- ---- ---- --------------------------------- 568** <15:13> 3 SET_EN RW,1 Set enable 569** <12> 1 BLK_SIZE RW,1 Scache/Bcache block size select 570** <11:08> 4 FB_DP RW,0 Force bad data parity 571** <07:02> 6 TAG_STAT RW Tag status and parity 572** <1> 1 FLUSH RW,0 If set, clear all tag valid bits 573** <0> 1 FHIT RW,0 Force hits 574** 575*/ 576 577#define SC_V_SET_EN 13 578#define SC_M_SET_EN (7<<SC_V_SET_EN) 579#define SC_V_BLK_SIZE 12 580#define SC_M_BLK_SIZE (1<<SC_V_BLK_SIZE) 581#define SC_V_FB_DP 8 582#define SC_M_FB_DP (0xF<<SC_V_FB_DP) 583#define SC_V_TAG_STAT 2 584#define SC_M_TAG_STAT (0x3F<<SC_V_TAG_STAT) 585#define SC_V_FLUSH 1 586#define SC_M_FLUSH (1<<SC_V_FLUSH) 587#define SC_V_FHIT 0 588#define SC_M_FHIT (1<<SC_V_FHIT) 589 590/* 591** 592** Bcache Control Register (BC_CTL) Bit Summary 593** 594** Extent Size Name Type Function 595** ------ ---- ---- ---- --------------------------------- 596** <27> 1 DIS_VIC_BUF WO,0 Disable Scache victim buffer 597** <26> 1 DIS_BAF_BYP WO,0 Disable speculative Bcache reads 598** <25> 1 DBG_MUX_SEL WO,0 Debug MUX select 599** <24:19> 6 PM_MUX_SEL WO,0 Performance counter MUX select 600** <18:17> 2 BC_WAVE WO,0 Number of cycles of wave pipelining 601** <16> 1 TL_PIPE_LATCH WO,0 Pipe system control pins 602** <15> 1 EI_DIS_ERR WO,1 Disable ECC (parity) error 603** <14:13> 2 BC_BAD_DAT WO,0 Force bad data 604** <12:08> 5 BC_TAG_STAT WO Bcache tag status and parity 605** <7> 1 BC_FHIT WO,0 Bcache force hit 606** <6> 1 EI_ECC WO,1 ECC or byte parity mode 607** <5> 1 VTM_FIRST WO,1 Drive out victim block address first 608** <4> 1 CORR_FILL_DAT WO,1 Correct fill data 609** <3> 1 EI_CMD_GRP3 WO,0 Drive MB command to external pins 610** <2> 1 EI_CMD_GRP2 WO,0 Drive LOCK & SET_DIRTY to ext. pins 611** <1> 1 ALLOC_CYC WO,0 Allocate cycle for non-cached LDs. 612** <0> 1 BC_ENA W0,0 Bcache enable 613** 614*/ 615#define BC_V_DIS_SC_VIC_BUF 27 616#define BC_M_DIS_SC_VIC_BUF (1<<BC_V_DIS_SC_VIC_BUF) 617#define BC_V_DIS_BAF_BYP 26 618#define BC_M_DIS_BAF_BYP (1<<BC_V_DIS_BAF_BYP) 619#define BC_V_DBG_MUX_SEL 25 620#define BC_M_DBG_MUX_SEL (1<<BC_V_DBG_MUX_SEL) 621#define BC_V_PM_MUX_SEL 19 622#define BC_M_PM_MUX_SEL (0x3F<<BC_V_PM_MUX_SEL) 623#define BC_V_BC_WAVE 17 624#define BC_M_BC_WAVE (3<<BC_V_BC_WAVE) 625#define BC_V_TL_PIPE_LATCH 16 626#define BC_M_TL_PIPE_LATCH (1<<BC_V_TL_PIPE_LATCH) 627#define BC_V_EI_DIS_ERR 15 628#define BC_M_EI_DIS_ERR (1<<BC_V_EI_DIS_ERR) 629#define BC_V_BC_BAD_DAT 13 630#define BC_M_BC_BAD_DAT (3<<BC_V_BC_BAD_DAT) 631#define BC_V_BC_TAG_STAT 8 632#define BC_M_BC_TAG_STAT (0x1F<<BC_V_BC_TAG_STAT) 633#define BC_V_BC_FHIT 7 634#define BC_M_BC_FHIT (1<<BC_V_BC_FHIT) 635#define BC_V_EI_ECC_OR_PARITY 6 636#define BC_M_EI_ECC_OR_PARITY (1<<BC_V_EI_ECC_OR_PARITY) 637#define BC_V_VTM_FIRST 5 638#define BC_M_VTM_FIRST (1<<BC_V_VTM_FIRST) 639#define BC_V_CORR_FILL_DAT 4 640#define BC_M_CORR_FILL_DAT (1<<BC_V_CORR_FILL_DAT) 641#define BC_V_EI_CMD_GRP3 3 642#define BC_M_EI_CMD_GRP3 (1<<BC_V_EI_CMD_GRP3) 643#define BC_V_EI_CMD_GRP2 2 644#define BC_M_EI_CMD_GRP2 (1<<BC_V_EI_CMD_GRP2) 645#define BC_V_ALLOC_CYC 1 646#define BC_M_ALLOC_CYC (1<<BC_V_ALLOC_CYC) 647#define BC_V_BC_ENA 0 648#define BC_M_BC_ENA (1<<BC_V_BC_ENA) 649 650#define BC_K_DFAULT \ 651 (((BC_M_EI_DIS_ERR) | \ 652 (BC_M_EI_ECC_OR_PARITY) | \ 653 (BC_M_VTM_FIRST) | \ 654 (BC_M_CORR_FILL_DAT))>>1) 655/* 656** 657** Bcache Configuration Register (BC_CONFIG) Bit Summary 658** 659** Extent Size Name Type Function 660** ------ ---- ---- ---- --------------------------------- 661** <35:29> 7 RSVD WO Reserved - Must Be Zero 662** <28:20> 9 WE_CTL WO,0 Bcache write enable control 663** <19:19> 1 RSVD WO,0 Reserved - Must Be Zero 664** <18:16> 3 WE_OFF WO,1 Bcache fill write enable pulse offset 665** <15:15> 1 RSVD WO,0 Reserved - Must Be Zero 666** <14:12> 3 RD_WR_SPC WO,7 Bcache private read/write spacing 667** <11:08> 4 WR_SPD WO,4 Bcache write speed in CPU cycles 668** <07:04> 4 RD_SPD WO,4 Bcache read speed in CPU cycles 669** <03:03> 1 RSVD WO,0 Reserved - Must Be Zero 670** <02:00> 3 SIZE WO,1 Bcache size 671*/ 672#define BC_V_WE_CTL 20 673#define BC_M_WE_CTL (0x1FF<<BC_V_WE_CTL) 674#define BC_V_WE_OFF 16 675#define BC_M_WE_OFF (0x7<<BC_V_WE_OFF) 676#define BC_V_RD_WR_SPC 12 677#define BC_M_RD_WR_SPC (0x7<<BC_V_RD_WR_SPC) 678#define BC_V_WR_SPD 8 679#define BC_M_WR_SPD (0xF<<BC_V_WR_SPD) 680#define BC_V_RD_SPD 4 681#define BC_M_RD_SPD (0xF<<BC_V_RD_SPD) 682#define BC_V_SIZE 0 683#define BC_M_SIZE (0x7<<BC_V_SIZE) 684 685#define BC_K_CONFIG \ 686 ((0x1<<BC_V_WE_OFF) | \ 687 (0x7<<BC_V_RD_WR_SPC) | \ 688 (0x4<<BC_V_WR_SPD) | \ 689 (0x4<<BC_V_RD_SPD) | \ 690 (0x1<<BC_V_SIZE)) 691 692/* 693** 694** DECchip 21164 Privileged Architecture Library Entry Offsets: 695** 696** Entry Name Offset (Hex) 697** 698** RESET 0000 699** IACCVIO 0080 700** INTERRUPT 0100 701** ITB_MISS 0180 702** DTB_MISS (Single) 0200 703** DTB_MISS (Double) 0280 704** UNALIGN 0300 705** D_FAULT 0380 706** MCHK 0400 707** OPCDEC 0480 708** ARITH 0500 709** FEN 0580 710** CALL_PAL (Privileged) 2000 711** CALL_PAL (Unprivileged) 3000 712** 713*/ 714 715#define PAL_RESET_ENTRY 0x0000 716#define PAL_IACCVIO_ENTRY 0x0080 717#define PAL_INTERRUPT_ENTRY 0x0100 718#define PAL_ITB_MISS_ENTRY 0x0180 719#define PAL_DTB_MISS_ENTRY 0x0200 720#define PAL_DOUBLE_MISS_ENTRY 0x0280 721#define PAL_UNALIGN_ENTRY 0x0300 722#define PAL_D_FAULT_ENTRY 0x0380 723#define PAL_MCHK_ENTRY 0x0400 724#define PAL_OPCDEC_ENTRY 0x0480 725#define PAL_ARITH_ENTRY 0x0500 726#define PAL_FEN_ENTRY 0x0580 727#define PAL_CALL_PAL_PRIV_ENTRY 0x2000 728#define PAL_CALL_PAL_UNPRIV_ENTRY 0x3000 729 730/* 731** 732** Architecturally Reserved Opcode (PALRES) Definitions: 733** 734*/ 735 736#define mtpr hw_mtpr 737#define mfpr hw_mfpr 738 739#define ldl_a hw_ldl/a 740#define ldq_a hw_ldq/a 741#define stq_a hw_stq/a 742#define stl_a hw_stl/a 743 744#define ldl_p hw_ldl/p 745#define ldq_p hw_ldq/p 746#define stl_p hw_stl/p 747#define stq_p hw_stq/p 748 749/* 750** Virtual PTE fetch variants of HW_LD. 751*/ 752#define ld_vpte hw_ldq/v 753 754/* 755** Physical mode load-lock and store-conditional variants of 756** HW_LD and HW_ST. 757*/ 758 759#define ldq_lp hw_ldq/pl 760#define stq_cp hw_stq/pc 761 762/* 763** 764** General Purpose Register Definitions: 765** 766*/ 767 768#define r0 $0 769#define r1 $1 770#define r2 $2 771#define r3 $3 772#define r4 $4 773#define r5 $5 774#define r6 $6 775#define r7 $7 776#define r8 $8 777#define r9 $9 778#define r10 $10 779#define r11 $11 780#define r12 $12 781#define r13 $13 782#define r14 $14 783#define r15 $15 784#define r16 $16 785#define r17 $17 786#define r18 $18 787#define r19 $19 788#define r20 $20 789#define r21 $21 790#define r22 $22 791#define r23 $23 792#define r24 $24 793#define r25 $25 794#define r26 $26 795#define r27 $27 796#define r28 $28 797#define r29 $29 798#define r30 $30 799#define r31 $31 800 801/* 802** 803** Floating Point Register Definitions: 804** 805*/ 806 807#define f0 $f0 808#define f1 $f1 809#define f2 $f2 810#define f3 $f3 811#define f4 $f4 812#define f5 $f5 813#define f6 $f6 814#define f7 $f7 815#define f8 $f8 816#define f9 $f9 817#define f10 $f10 818#define f11 $f11 819#define f12 $f12 820#define f13 $f13 821#define f14 $f14 822#define f15 $f15 823#define f16 $f16 824#define f17 $f17 825#define f18 $f18 826#define f19 $f19 827#define f20 $f20 828#define f21 $f21 829#define f22 $f22 830#define f23 $f23 831#define f24 $f24 832#define f25 $f25 833#define f26 $f26 834#define f27 $f27 835#define f28 $f28 836#define f29 $f29 837#define f30 $f30 838#define f31 $f31 839 840/* 841** 842** PAL Temporary Register Definitions: 843** 844*/ 845 846// covered by fetch distribution..pb Nov/95 847 848// #define pt0 0x140 849// #define pt1 0x141 850// #define pt2 0x142 851// #define pt3 0x143 852// #define pt4 0x144 853// #define pt5 0x145 854// #define pt6 0x146 855// #define pt7 0x147 856// #define pt8 0x148 857// #define pt9 0x149 858// #define pt10 0x14A 859// #define pt11 0x14B 860// #define pt12 0x14C 861// #define pt13 0x14D 862// #define pt14 0x14E 863// #define pt15 0x14F 864// #define pt16 0x150 865// #define pt17 0x151 866// #define pt18 0x152 867// #define pt19 0x153 868// #define pt20 0x154 869// #define pt21 0x155 870// #define pt22 0x156 871// #define pt23 0x157 872 873/* 874** PAL Shadow Registers: 875** 876** The DECchip 21164 shadows r8-r14 and r25 when in PALmode and 877** ICSR<SDE> = 1. 878*/ 879 880#define p0 r8 /* ITB/DTB Miss Scratch */ 881#define p1 r9 /* ITB/DTB Miss Scratch */ 882#define p2 r10 /* ITB/DTB Miss Scratch */ 883#define p3 r11 884// #define ps r11 /* Processor Status */ 885#define p4 r12 /* Local Scratch */ 886#define p5 r13 /* Local Scratch */ 887#define p6 r14 /* Local Scratch */ 888#define p7 r25 /* Local Scratch */ 889 890/* 891** SRM Defined State Definitions: 892*/ 893 894/* 895** This table is an accounting of the DECchip 21164 storage used to 896** implement the SRM defined state for OSF/1. 897** 898** IPR Name Internal Storage 899** -------- ---------------- 900** Processor Status ps, dtbCm, ipl, r11 901** Program Counter Ibox 902** Interrupt Entry ptEntInt 903** Arith Trap Entry ptEntArith 904** MM Fault Entry ptEntMM 905** Unaligned Access Entry ptEntUna 906** Instruction Fault Entry ptEntIF 907** Call System Entry ptEntSys 908** User Stack Pointer ptUsp 909** Kernel Stack Pointer ptKsp 910** Kernel Global Pointer ptKgp 911** System Value ptSysVal 912** Page Table Base Register ptPtbr 913** Virtual Page Table Base iVptBr, mVptBr 914** Process Control Block Base ptPcbb 915** Address Space Number itbAsn, dtbAsn 916** Cycle Counter cc, ccCtl 917** Float Point Enable icsr 918** Lock Flag Cbox/System 919** Unique PCB 920** Who-Am-I ptWhami 921*/ 922 923#define ptEntUna pt2 /* Unaligned Access Dispatch Entry */ 924#define ptImpure pt3 /* Pointer To PAL Scratch Area */ 925#define ptEntIF pt7 /* Instruction Fault Dispatch Entry */ 926#define ptIntMask pt8 /* Interrupt Enable Mask */ 927#define ptEntSys pt9 /* Call System Dispatch Entry */ 928#define ptTrap pt11 929#define ptEntInt pt11 /* Hardware Interrupt Dispatch Entry */ 930#define ptEntArith pt12 /* Arithmetic Trap Dispatch Entry */ 931#if defined(KDEBUG) 932#define ptEntDbg pt13 /* Kernel Debugger Dispatch Entry */ 933#endif /* KDEBUG */ 934#define ptMisc pt16 /* Miscellaneous Flags */ 935#define ptWhami pt16 /* Who-Am-I Register Pt16<15:8> */ 936#define ptMces pt16 /* Machine Check Error Summary Pt16<4:0> */ 937#define ptSysVal pt17 /* Per-Processor System Value */ 938#define ptUsp pt18 /* User Stack Pointer */ 939#define ptKsp pt19 /* Kernel Stack Pointer */ 940#define ptPtbr pt20 /* Page Table Base Register */ 941#define ptEntMM pt21 /* MM Fault Dispatch Entry */ 942#define ptKgp pt22 /* Kernel Global Pointer */ 943#define ptPcbb pt23 /* Process Control Block Base */ 944 945/* 946** 947** Miscellaneous PAL State Flags (ptMisc) Bit Summary 948** 949** Extent Size Name Function 950** ------ ---- ---- --------------------------------- 951** <55:48> 8 SWAP Swap PALcode flag -- character 'S' 952** <47:32> 16 MCHK Machine Check Error code 953** <31:16> 16 SCB System Control Block vector 954** <15:08> 8 WHAMI Who-Am-I identifier 955** <04:00> 5 MCES Machine Check Error Summary bits 956** 957*/ 958 959#define PT16_V_MCES 0 960#define PT16_V_WHAMI 8 961#define PT16_V_SCB 16 962#define PT16_V_MCHK 32 963#define PT16_V_SWAP 48 964 965#endif /* DC21164FROMGASSOURCES_INCLUDED */ 966