dc21164FromGasSources.h revision 8029
18012Ssaidi@eecs.umich.edu/* 28029Snate@binkert.org * Copyright (c) 1993 The Hewlett-Packard Development Company 38029Snate@binkert.org * All rights reserved. 48013Sbinkertn@umich.edu * 58029Snate@binkert.org * Redistribution and use in source and binary forms, with or without 68029Snate@binkert.org * modification, are permitted provided that the following conditions are 78029Snate@binkert.org * met: redistributions of source code must retain the above copyright 88029Snate@binkert.org * notice, this list of conditions and the following disclaimer; 98029Snate@binkert.org * redistributions in binary form must reproduce the above copyright 108029Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 118029Snate@binkert.org * documentation and/or other materials provided with the distribution; 128029Snate@binkert.org * neither the name of the copyright holders nor the names of its 138029Snate@binkert.org * contributors may be used to endorse or promote products derived from 148029Snate@binkert.org * this software without specific prior written permission. 158013Sbinkertn@umich.edu * 168029Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 178029Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 188029Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 198029Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 208029Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 218029Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 228029Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 238029Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 248029Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 258029Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 268029Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 278013Sbinkertn@umich.edu */ 288012Ssaidi@eecs.umich.edu 297997Ssaidi@eecs.umich.edu#ifndef DC21164FROMGASSOURCES_INCLUDED 307997Ssaidi@eecs.umich.edu#define DC21164FROMGASSOURCES_INCLUDED 1 317997Ssaidi@eecs.umich.edu 327997Ssaidi@eecs.umich.edu/* 337997Ssaidi@eecs.umich.edu** 347997Ssaidi@eecs.umich.edu** INTERNAL PROCESSOR REGISTER DEFINITIONS 357997Ssaidi@eecs.umich.edu** 367997Ssaidi@eecs.umich.edu** The internal processor register definitions below are annotated 377997Ssaidi@eecs.umich.edu** with one of the following symbols: 387997Ssaidi@eecs.umich.edu** 397997Ssaidi@eecs.umich.edu** RW - The register may be read and written 407997Ssaidi@eecs.umich.edu** RO - The register may only be read 417997Ssaidi@eecs.umich.edu** WO - The register may only be written 427997Ssaidi@eecs.umich.edu** 437997Ssaidi@eecs.umich.edu** For RO and WO registers, all bits and fields within the register are 447997Ssaidi@eecs.umich.edu** also read-only or write-only. For RW registers, each bit or field 457997Ssaidi@eecs.umich.edu** within the register is annotated with one of the following: 467997Ssaidi@eecs.umich.edu** 477997Ssaidi@eecs.umich.edu** RW - The bit/field may be read and written 487997Ssaidi@eecs.umich.edu** RO - The bit/field may be read; writes are ignored 497997Ssaidi@eecs.umich.edu** WO - The bit/field may be written; reads return UNPREDICTABLE 507997Ssaidi@eecs.umich.edu** WZ - The bit/field may be written; reads return a zero value 517997Ssaidi@eecs.umich.edu** W0C - The bit/field may be read; write-zero-to-clear 527997Ssaidi@eecs.umich.edu** W1C - The bit/field may be read; write-one-to-clear 537997Ssaidi@eecs.umich.edu** WA - The bit/field may be read; write-anything-to-clear 547997Ssaidi@eecs.umich.edu** RC - The bit/field may be read, causing state to clear; 557997Ssaidi@eecs.umich.edu** writes are ignored 567997Ssaidi@eecs.umich.edu** 577997Ssaidi@eecs.umich.edu*/ 587997Ssaidi@eecs.umich.edu 597997Ssaidi@eecs.umich.edu 607997Ssaidi@eecs.umich.edu/* 617997Ssaidi@eecs.umich.edu** 627997Ssaidi@eecs.umich.edu** Ibox IPR Definitions: 637997Ssaidi@eecs.umich.edu** 647997Ssaidi@eecs.umich.edu*/ 657997Ssaidi@eecs.umich.edu 667997Ssaidi@eecs.umich.edu// replaced by ev5_defs.h #define isr 0x100 /* RO - Interrupt Summary */ 677997Ssaidi@eecs.umich.edu#define itbTag 0x101 /* WO - ITB Tag */ 687997Ssaidi@eecs.umich.edu#define itbPte 0x102 /* RW - ITB Page Table Entry */ 697997Ssaidi@eecs.umich.edu#define itbAsn 0x103 /* RW - ITB Address Space Number */ 707997Ssaidi@eecs.umich.edu#define itbPteTemp 0x104 /* RO - ITB Page Table Entry Temporary */ 717997Ssaidi@eecs.umich.edu#define itbIa 0x105 /* WO - ITB Invalidate All */ 727997Ssaidi@eecs.umich.edu#define itbIap 0x106 /* WO - ITB Invalidate All Process */ 737997Ssaidi@eecs.umich.edu#define itbIs 0x107 /* WO - ITB Invalidate Single */ 747997Ssaidi@eecs.umich.edu// replaced by ev5_defs.h #define sirr 0x108 /* RW - Software Interrupt Request */ 757997Ssaidi@eecs.umich.edu// replaced by ev5_defs.h #define astrr 0x109 /* RW - Async. System Trap Request */ 767997Ssaidi@eecs.umich.edu// replaced by ev5_defs.h #define aster 0x10A /* RW - Async. System Trap Enable */ 777997Ssaidi@eecs.umich.edu#define excAddr 0x10B /* RW - Exception Address */ 787997Ssaidi@eecs.umich.edu#define excSum 0x10C /* RW - Exception Summary */ 797997Ssaidi@eecs.umich.edu#define excMask 0x10D /* RO - Exception Mask */ 807997Ssaidi@eecs.umich.edu#define palBase 0x10E /* RW - PAL Base */ 817997Ssaidi@eecs.umich.edu#define ips 0x10F /* RW - Processor Status */ 827997Ssaidi@eecs.umich.edu// replaced by ev5_defs.h #define ipl 0x110 /* RW - Interrupt Priority Level */ 837997Ssaidi@eecs.umich.edu#define intId 0x111 /* RO - Interrupt ID */ 847997Ssaidi@eecs.umich.edu#define iFaultVaForm 0x112 /* RO - Formatted Faulting VA */ 857997Ssaidi@eecs.umich.edu#define iVptBr 0x113 /* RW - I-Stream Virtual Page Table Base */ 867997Ssaidi@eecs.umich.edu#define hwIntClr 0x115 /* WO - Hardware Interrupt Clear */ 877997Ssaidi@eecs.umich.edu#define slXmit 0x116 /* WO - Serial Line Transmit */ 887997Ssaidi@eecs.umich.edu#define slRcv 0x117 /* RO - Serial Line Receive */ 897997Ssaidi@eecs.umich.edu// replaced by ev5_defs.h #define icsr 0x118 /* RW - Ibox Control/Status */ 907997Ssaidi@eecs.umich.edu#define icFlush 0x119 /* WO - I-Cache Flush Control */ 917997Ssaidi@eecs.umich.edu#define flushIc 0x119 /* WO - I-Cache Flush Control (DC21064 Symbol) */ 927997Ssaidi@eecs.umich.edu#define icPerr 0x11A /* RW - I-Cache Parity Error Status */ 937997Ssaidi@eecs.umich.edu#define PmCtr 0x11C /* RW - Performance Counter */ 947997Ssaidi@eecs.umich.edu 957997Ssaidi@eecs.umich.edu/* 967997Ssaidi@eecs.umich.edu** 977997Ssaidi@eecs.umich.edu** Ibox Control/Status Register (ICSR) Bit Summary 987997Ssaidi@eecs.umich.edu** 997997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 1007997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- ------------------------------------ 1017997Ssaidi@eecs.umich.edu** <39> 1 TST RW,0 Assert Test Status 1027997Ssaidi@eecs.umich.edu** <38> 1 ISTA RO I-Cache BIST Status 1037997Ssaidi@eecs.umich.edu** <37> 1 DBS RW,1 Debug Port Select 1047997Ssaidi@eecs.umich.edu** <36> 1 FBD RW,0 Force Bad I-Cache Data Parity 1057997Ssaidi@eecs.umich.edu** <35> 1 FBT RW,0 Force Bad I-Cache Tag Parity 1067997Ssaidi@eecs.umich.edu** <34> 1 FMS RW,0 Force I-Cache Miss 1077997Ssaidi@eecs.umich.edu** <33> 1 SLE RW,0 Enable Serial Line Interrupts 1087997Ssaidi@eecs.umich.edu** <32> 1 CRDE RW,0 Enable Correctable Error Interrupts 1097997Ssaidi@eecs.umich.edu** <30> 1 SDE RW,0 Enable PAL Shadow Registers 1107997Ssaidi@eecs.umich.edu** <29:28> 2 SPE RW,0 Enable I-Stream Super Page Mode 1117997Ssaidi@eecs.umich.edu** <27> 1 HWE RW,0 Enable PALRES Instrs in Kernel Mode 1127997Ssaidi@eecs.umich.edu** <26> 1 FPE RW,0 Enable Floating Point Instructions 1137997Ssaidi@eecs.umich.edu** <25> 1 TMD RW,0 Disable Ibox Timeout Counter 1147997Ssaidi@eecs.umich.edu** <24> 1 TMM RW,0 Timeout Counter Mode 1157997Ssaidi@eecs.umich.edu** 1167997Ssaidi@eecs.umich.edu*/ 1177997Ssaidi@eecs.umich.edu 1187997Ssaidi@eecs.umich.edu#define ICSR_V_TST 39 1197997Ssaidi@eecs.umich.edu#define ICSR_M_TST (1<<ICSR_V_TST) 1207997Ssaidi@eecs.umich.edu#define ICSR_V_ISTA 38 1217997Ssaidi@eecs.umich.edu#define ICSR_M_ISTA (1<<ICSR_V_ISTA) 1227997Ssaidi@eecs.umich.edu#define ICSR_V_DBS 37 1237997Ssaidi@eecs.umich.edu#define ICSR_M_DBS (1<<ICSR_V_DBS) 1247997Ssaidi@eecs.umich.edu#define ICSR_V_FBD 36 1257997Ssaidi@eecs.umich.edu#define ICSR_M_FBD (1<<ICSR_V_FBD) 1267997Ssaidi@eecs.umich.edu#define ICSR_V_FBT 35 1277997Ssaidi@eecs.umich.edu#define ICSR_M_FBT (1<<ICSR_V_FBT) 1287997Ssaidi@eecs.umich.edu#define ICSR_V_FMS 34 1297997Ssaidi@eecs.umich.edu#define ICSR_M_FMS (1<<ICSR_V_FMS) 1307997Ssaidi@eecs.umich.edu#define ICSR_V_SLE 33 1317997Ssaidi@eecs.umich.edu#define ICSR_M_SLE (1<<ICSR_V_SLE) 1327997Ssaidi@eecs.umich.edu#define ICSR_V_CRDE 32 1337997Ssaidi@eecs.umich.edu#define ICSR_M_CRDE (1<<ICSR_V_CRDE) 1347997Ssaidi@eecs.umich.edu#define ICSR_V_SDE 30 1357997Ssaidi@eecs.umich.edu#define ICSR_M_SDE (1<<ICSR_V_SDE) 1367997Ssaidi@eecs.umich.edu#define ICSR_V_SPE 28 1377997Ssaidi@eecs.umich.edu#define ICSR_M_SPE (3<<ICSR_V_SPE) 1387997Ssaidi@eecs.umich.edu#define ICSR_V_HWE 27 1397997Ssaidi@eecs.umich.edu#define ICSR_M_HWE (1<<ICSR_V_HWE) 1407997Ssaidi@eecs.umich.edu#define ICSR_V_FPE 26 1417997Ssaidi@eecs.umich.edu#define ICSR_M_FPE (1<<ICSR_V_FPE) 1427997Ssaidi@eecs.umich.edu#define ICSR_V_TMD 25 1437997Ssaidi@eecs.umich.edu#define ICSR_M_TMD (1<<ICSR_V_TMD) 1447997Ssaidi@eecs.umich.edu#define ICSR_V_TMM 24 1457997Ssaidi@eecs.umich.edu#define ICSR_M_TMM (1<<ICSR_V_TMM) 1467997Ssaidi@eecs.umich.edu 1477997Ssaidi@eecs.umich.edu/* 1487997Ssaidi@eecs.umich.edu** 1497997Ssaidi@eecs.umich.edu** Serial Line Tranmit Register (SL_XMIT) 1507997Ssaidi@eecs.umich.edu** 1517997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 1527997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- ------------------------------------ 1537997Ssaidi@eecs.umich.edu** <7> 1 TMT WO,1 Serial line transmit data 1547997Ssaidi@eecs.umich.edu** 1557997Ssaidi@eecs.umich.edu*/ 1567997Ssaidi@eecs.umich.edu 1577997Ssaidi@eecs.umich.edu#define SLXMIT_V_TMT 7 1587997Ssaidi@eecs.umich.edu#define SLXMIT_M_TMT (1<<SLXMIT_V_TMT) 1597997Ssaidi@eecs.umich.edu 1607997Ssaidi@eecs.umich.edu/* 1617997Ssaidi@eecs.umich.edu** 1627997Ssaidi@eecs.umich.edu** Serial Line Receive Register (SL_RCV) 1637997Ssaidi@eecs.umich.edu** 1647997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 1657997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- ------------------------------------ 1667997Ssaidi@eecs.umich.edu** <6> 1 RCV RO Serial line receive data 1677997Ssaidi@eecs.umich.edu** 1687997Ssaidi@eecs.umich.edu*/ 1697997Ssaidi@eecs.umich.edu 1707997Ssaidi@eecs.umich.edu#define SLRCV_V_RCV 6 1717997Ssaidi@eecs.umich.edu#define SLRCV_M_RCV (1<<SLRCV_V_RCV) 1727997Ssaidi@eecs.umich.edu 1737997Ssaidi@eecs.umich.edu/* 1747997Ssaidi@eecs.umich.edu** 1757997Ssaidi@eecs.umich.edu** Icache Parity Error Status Register (ICPERR) Bit Summary 1767997Ssaidi@eecs.umich.edu** 1777997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 1787997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- ------------------------------------ 1797997Ssaidi@eecs.umich.edu** <13> 1 TMR W1C Timeout reset error 1807997Ssaidi@eecs.umich.edu** <12> 1 TPE W1C Tag parity error 1817997Ssaidi@eecs.umich.edu** <11> 1 DPE W1C Data parity error 1827997Ssaidi@eecs.umich.edu** 1837997Ssaidi@eecs.umich.edu*/ 1847997Ssaidi@eecs.umich.edu 1857997Ssaidi@eecs.umich.edu#define ICPERR_V_TMR 13 1867997Ssaidi@eecs.umich.edu#define ICPERR_M_TMR (1<<ICPERR_V_TMR) 1877997Ssaidi@eecs.umich.edu#define ICPERR_V_TPE 12 1887997Ssaidi@eecs.umich.edu#define ICPERR_M_TPE (1<<ICPERR_V_TPE) 1897997Ssaidi@eecs.umich.edu#define ICPERR_V_DPE 11 1907997Ssaidi@eecs.umich.edu#define ICPERR_M_DPE (1<<ICPERR_V_DPE) 1917997Ssaidi@eecs.umich.edu 1927997Ssaidi@eecs.umich.edu#define ICPERR_M_ALL (ICPERR_M_TMR | ICPERR_M_TPE | ICPERR_M_DPE) 1937997Ssaidi@eecs.umich.edu 1947997Ssaidi@eecs.umich.edu/* 1957997Ssaidi@eecs.umich.edu** 1967997Ssaidi@eecs.umich.edu** Exception Summary Register (EXC_SUM) Bit Summary 1977997Ssaidi@eecs.umich.edu** 1987997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 1997997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- ------------------------------------ 2007997Ssaidi@eecs.umich.edu** <16> 1 IOV WA Integer overflow 2017997Ssaidi@eecs.umich.edu** <15> 1 INE WA Inexact result 2027997Ssaidi@eecs.umich.edu** <14> 1 UNF WA Underflow 2037997Ssaidi@eecs.umich.edu** <13> 1 FOV WA Overflow 2047997Ssaidi@eecs.umich.edu** <12> 1 DZE WA Division by zero 2057997Ssaidi@eecs.umich.edu** <11> 1 INV WA Invalid operation 2067997Ssaidi@eecs.umich.edu** <10> 1 SWC WA Software completion 2077997Ssaidi@eecs.umich.edu** 2087997Ssaidi@eecs.umich.edu*/ 2097997Ssaidi@eecs.umich.edu 2107997Ssaidi@eecs.umich.edu#define EXC_V_IOV 16 2117997Ssaidi@eecs.umich.edu#define EXC_M_IOV (1<<EXC_V_IOV) 2127997Ssaidi@eecs.umich.edu#define EXC_V_INE 15 2137997Ssaidi@eecs.umich.edu#define EXC_M_INE (1<<EXC_V_INE) 2147997Ssaidi@eecs.umich.edu#define EXC_V_UNF 14 2157997Ssaidi@eecs.umich.edu#define EXC_M_UNF (1<<EXC_V_UNF) 2167997Ssaidi@eecs.umich.edu#define EXC_V_FOV 13 2177997Ssaidi@eecs.umich.edu#define EXC_M_FOV (1<<EXC_V_FOV) 2187997Ssaidi@eecs.umich.edu#define EXC_V_DZE 12 2197997Ssaidi@eecs.umich.edu#define EXC_M_DZE (1<<EXC_V_DZE) 2207997Ssaidi@eecs.umich.edu#define EXC_V_INV 11 2217997Ssaidi@eecs.umich.edu#define EXC_M_INV (1<<EXC_V_INV) 2227997Ssaidi@eecs.umich.edu#define EXC_V_SWC 10 2237997Ssaidi@eecs.umich.edu#define EXC_M_SWC (1<<EXC_V_SWC) 2247997Ssaidi@eecs.umich.edu 2257997Ssaidi@eecs.umich.edu/* 2267997Ssaidi@eecs.umich.edu** 2277997Ssaidi@eecs.umich.edu** Hardware Interrupt Clear Register (HWINT_CLR) Bit Summary 2287997Ssaidi@eecs.umich.edu** 2297997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 2307997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- --------------------------------- 2317997Ssaidi@eecs.umich.edu** <33> 1 SLC W1C Clear Serial Line interrupt 2327997Ssaidi@eecs.umich.edu** <32> 1 CRDC W1C Clear Correctable Read Data interrupt 2337997Ssaidi@eecs.umich.edu** <29> 1 PC2C W1C Clear Performance Counter 2 interrupt 2347997Ssaidi@eecs.umich.edu** <28> 1 PC1C W1C Clear Performance Counter 1 interrupt 2357997Ssaidi@eecs.umich.edu** <27> 1 PC0C W1C Clear Performance Counter 0 interrupt 2367997Ssaidi@eecs.umich.edu** 2377997Ssaidi@eecs.umich.edu*/ 2387997Ssaidi@eecs.umich.edu 2397997Ssaidi@eecs.umich.edu#define HWINT_V_SLC 33 2407997Ssaidi@eecs.umich.edu#define HWINT_M_SLC (1<<HWINT_V_SLC) 2417997Ssaidi@eecs.umich.edu#define HWINT_V_CRDC 32 2427997Ssaidi@eecs.umich.edu#define HWINT_M_CRDC (1<<HWINT_V_CRDC) 2437997Ssaidi@eecs.umich.edu#define HWINT_V_PC2C 29 2447997Ssaidi@eecs.umich.edu#define HWINT_M_PC2C (1<<HWINT_V_PC2C) 2457997Ssaidi@eecs.umich.edu#define HWINT_V_PC1C 28 2467997Ssaidi@eecs.umich.edu#define HWINT_M_PC1C (1<<HWINT_V_PC1C) 2477997Ssaidi@eecs.umich.edu#define HWINT_V_PC0C 27 2487997Ssaidi@eecs.umich.edu#define HWINT_M_PC0C (1<<HWINT_V_PC0C) 2497997Ssaidi@eecs.umich.edu 2507997Ssaidi@eecs.umich.edu/* 2517997Ssaidi@eecs.umich.edu** 2527997Ssaidi@eecs.umich.edu** Interrupt Summary Register (ISR) Bit Summary 2537997Ssaidi@eecs.umich.edu** 2547997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 2557997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- --------------------------------- 2567997Ssaidi@eecs.umich.edu** <34> 1 HLT RO External Halt interrupt 2577997Ssaidi@eecs.umich.edu** <33> 1 SLI RO Serial Line interrupt 2587997Ssaidi@eecs.umich.edu** <32> 1 CRD RO Correctable ECC errors 2597997Ssaidi@eecs.umich.edu** <31> 1 MCK RO System Machine Check 2607997Ssaidi@eecs.umich.edu** <30> 1 PFL RO Power Fail 2617997Ssaidi@eecs.umich.edu** <29> 1 PC2 RO Performance Counter 2 interrupt 2627997Ssaidi@eecs.umich.edu** <28> 1 PC1 RO Performance Counter 1 interrupt 2637997Ssaidi@eecs.umich.edu** <27> 1 PC0 RO Performance Counter 0 interrupt 2647997Ssaidi@eecs.umich.edu** <23> 1 I23 RO External Hardware interrupt 2657997Ssaidi@eecs.umich.edu** <22> 1 I22 RO External Hardware interrupt 2667997Ssaidi@eecs.umich.edu** <21> 1 I21 RO External Hardware interrupt 2677997Ssaidi@eecs.umich.edu** <20> 1 I20 RO External Hardware interrupt 2687997Ssaidi@eecs.umich.edu** <19> 1 ATR RO Async. System Trap request 2697997Ssaidi@eecs.umich.edu** <18:4> 15 SIRR RO,0 Software Interrupt request 2707997Ssaidi@eecs.umich.edu** <3:0> 4 ASTRR RO Async. System Trap request (USEK) 2717997Ssaidi@eecs.umich.edu** 2727997Ssaidi@eecs.umich.edu**/ 2737997Ssaidi@eecs.umich.edu 2747997Ssaidi@eecs.umich.edu#define ISR_V_HLT 34 2757997Ssaidi@eecs.umich.edu#define ISR_M_HLT (1<<ISR_V_HLT) 2767997Ssaidi@eecs.umich.edu#define ISR_V_SLI 33 2777997Ssaidi@eecs.umich.edu#define ISR_M_SLI (1<<ISR_V_SLI) 2787997Ssaidi@eecs.umich.edu#define ISR_V_CRD 32 2797997Ssaidi@eecs.umich.edu#define ISR_M_CRD (1<<ISR_V_CRD) 2807997Ssaidi@eecs.umich.edu#define ISR_V_MCK 31 2817997Ssaidi@eecs.umich.edu#define ISR_M_MCK (1<<ISR_V_MCK) 2827997Ssaidi@eecs.umich.edu#define ISR_V_PFL 30 2837997Ssaidi@eecs.umich.edu#define ISR_M_PFL (1<<ISR_V_PFL) 2847997Ssaidi@eecs.umich.edu#define ISR_V_PC2 29 2857997Ssaidi@eecs.umich.edu#define ISR_M_PC2 (1<<ISR_V_PC2) 2867997Ssaidi@eecs.umich.edu#define ISR_V_PC1 28 2877997Ssaidi@eecs.umich.edu#define ISR_M_PC1 (1<<ISR_V_PC1) 2887997Ssaidi@eecs.umich.edu#define ISR_V_PC0 27 2897997Ssaidi@eecs.umich.edu#define ISR_M_PC0 (1<<ISR_V_PC0) 2907997Ssaidi@eecs.umich.edu#define ISR_V_I23 23 2917997Ssaidi@eecs.umich.edu#define ISR_M_I23 (1<<ISR_V_I23) 2927997Ssaidi@eecs.umich.edu#define ISR_V_I22 22 2937997Ssaidi@eecs.umich.edu#define ISR_M_I22 (1<<ISR_V_I22) 2947997Ssaidi@eecs.umich.edu#define ISR_V_I21 21 2957997Ssaidi@eecs.umich.edu#define ISR_M_I21 (1<<ISR_V_I21) 2967997Ssaidi@eecs.umich.edu#define ISR_V_I20 20 2977997Ssaidi@eecs.umich.edu#define ISR_M_I20 (1<<ISR_V_I20) 2987997Ssaidi@eecs.umich.edu#define ISR_V_ATR 19 2997997Ssaidi@eecs.umich.edu#define ISR_M_ATR (1<<ISR_V_ATR) 3007997Ssaidi@eecs.umich.edu#define ISR_V_SIRR 4 3017997Ssaidi@eecs.umich.edu#define ISR_M_SIRR (0x7FFF<<ISR_V_SIRR) 3027997Ssaidi@eecs.umich.edu#define ISR_V_ASTRR 0 3037997Ssaidi@eecs.umich.edu#define ISR_M_ASTRR (0xF<<ISR_V_ASTRR) 3047997Ssaidi@eecs.umich.edu 3057997Ssaidi@eecs.umich.edu/* 3067997Ssaidi@eecs.umich.edu** 3077997Ssaidi@eecs.umich.edu** Mbox and D-Cache IPR Definitions: 3087997Ssaidi@eecs.umich.edu** 3097997Ssaidi@eecs.umich.edu*/ 3107997Ssaidi@eecs.umich.edu 3117997Ssaidi@eecs.umich.edu#define dtbAsn 0x200 /* WO - DTB Address Space Number */ 3127997Ssaidi@eecs.umich.edu#define dtbCm 0x201 /* WO - DTB Current Mode */ 3137997Ssaidi@eecs.umich.edu#define dtbTag 0x202 /* WO - DTB Tag */ 3147997Ssaidi@eecs.umich.edu#define dtbPte 0x203 /* RW - DTB Page Table Entry */ 3157997Ssaidi@eecs.umich.edu#define dtbPteTemp 0x204 /* RO - DTB Page Table Entry Temporary */ 3167997Ssaidi@eecs.umich.edu#define mmStat 0x205 /* RO - D-Stream MM Fault Status */ 3177997Ssaidi@eecs.umich.edu// replaced by ev5_defs.h #define va 0x206 /* RO - Faulting Virtual Address */ 3187997Ssaidi@eecs.umich.edu#define vaForm 0x207 /* RO - Formatted Virtual Address */ 3197997Ssaidi@eecs.umich.edu#define mVptBr 0x208 /* WO - Mbox Virtual Page Table Base */ 3207997Ssaidi@eecs.umich.edu#define dtbIap 0x209 /* WO - DTB Invalidate All Process */ 3217997Ssaidi@eecs.umich.edu#define dtbIa 0x20A /* WO - DTB Invalidate All */ 3227997Ssaidi@eecs.umich.edu#define dtbIs 0x20B /* WO - DTB Invalidate Single */ 3237997Ssaidi@eecs.umich.edu#define altMode 0x20C /* WO - Alternate Mode */ 3247997Ssaidi@eecs.umich.edu// replaced by ev5_defs.h #define cc 0x20D /* WO - Cycle Counter */ 3257997Ssaidi@eecs.umich.edu#define ccCtl 0x20E /* WO - Cycle Counter Control */ 3267997Ssaidi@eecs.umich.edu// replaced by ev5_defs.h #define mcsr 0x20F /* RW - Mbox Control Register */ 3277997Ssaidi@eecs.umich.edu#define dcFlush 0x210 /* WO - Dcache Flush */ 3287997Ssaidi@eecs.umich.edu#define dcPerr 0x212 /* RW - Dcache Parity Error Status */ 3297997Ssaidi@eecs.umich.edu#define dcTestCtl 0x213 /* RW - Dcache Test Tag Control */ 3307997Ssaidi@eecs.umich.edu#define dcTestTag 0x214 /* RW - Dcache Test Tag */ 3317997Ssaidi@eecs.umich.edu#define dcTestTagTemp 0x215 /* RW - Dcache Test Tag Temporary */ 3327997Ssaidi@eecs.umich.edu#define dcMode 0x216 /* RW - Dcache Mode */ 3337997Ssaidi@eecs.umich.edu#define mafMode 0x217 /* RW - Miss Address File Mode */ 3347997Ssaidi@eecs.umich.edu 3357997Ssaidi@eecs.umich.edu/* 3367997Ssaidi@eecs.umich.edu** 3377997Ssaidi@eecs.umich.edu** D-Stream MM Fault Status Register (MM_STAT) Bit Summary 3387997Ssaidi@eecs.umich.edu** 3397997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 3407997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- --------------------------------- 3417997Ssaidi@eecs.umich.edu** <16:11> 6 OPCODE RO Opcode of faulting instruction 3427997Ssaidi@eecs.umich.edu** <10:06> 5 RA RO Ra field of faulting instruction 3437997Ssaidi@eecs.umich.edu** <5> 1 BAD_VA RO Bad virtual address 3447997Ssaidi@eecs.umich.edu** <4> 1 DTB_MISS RO Reference resulted in DTB miss 3457997Ssaidi@eecs.umich.edu** <3> 1 FOW RO Fault on write 3467997Ssaidi@eecs.umich.edu** <2> 1 FOR RO Fault on read 3477997Ssaidi@eecs.umich.edu** <1> 1 ACV RO Access violation 3487997Ssaidi@eecs.umich.edu** <0> 1 WR RO Reference type 3497997Ssaidi@eecs.umich.edu** 3507997Ssaidi@eecs.umich.edu*/ 3517997Ssaidi@eecs.umich.edu 3527997Ssaidi@eecs.umich.edu#define MMSTAT_V_OPC 11 3537997Ssaidi@eecs.umich.edu#define MMSTAT_M_OPC (0x3F<<MMSTAT_V_OPC) 3547997Ssaidi@eecs.umich.edu#define MMSTAT_V_RA 6 3557997Ssaidi@eecs.umich.edu#define MMSTAT_M_RA (0x1F<<MMSTAT_V_RA) 3567997Ssaidi@eecs.umich.edu#define MMSTAT_V_BAD_VA 5 3577997Ssaidi@eecs.umich.edu#define MMSTAT_M_BAD_VA (1<<MMSTAT_V_BAD_VA) 3587997Ssaidi@eecs.umich.edu#define MMSTAT_V_DTB_MISS 4 3597997Ssaidi@eecs.umich.edu#define MMSTAT_M_DTB_MISS (1<<MMSTAT_V_DTB_MISS) 3607997Ssaidi@eecs.umich.edu#define MMSTAT_V_FOW 3 3617997Ssaidi@eecs.umich.edu#define MMSTAT_M_FOW (1<<MMSTAT_V_FOW) 3627997Ssaidi@eecs.umich.edu#define MMSTAT_V_FOR 2 3637997Ssaidi@eecs.umich.edu#define MMSTAT_M_FOR (1<<MMSTAT_V_FOR) 3647997Ssaidi@eecs.umich.edu#define MMSTAT_V_ACV 1 3657997Ssaidi@eecs.umich.edu#define MMSTAT_M_ACV (1<<MMSTAT_V_ACV) 3667997Ssaidi@eecs.umich.edu#define MMSTAT_V_WR 0 3677997Ssaidi@eecs.umich.edu#define MMSTAT_M_WR (1<<MMSTAT_V_WR) 3687997Ssaidi@eecs.umich.edu 3697997Ssaidi@eecs.umich.edu 3707997Ssaidi@eecs.umich.edu/* 3717997Ssaidi@eecs.umich.edu** 3727997Ssaidi@eecs.umich.edu** Mbox Control Register (MCSR) Bit Summary 3737997Ssaidi@eecs.umich.edu** 3747997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 3757997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- --------------------------------- 3767997Ssaidi@eecs.umich.edu** <5> 1 DBG1 RW,0 Mbox Debug Packet Select 3777997Ssaidi@eecs.umich.edu** <4> 1 E_BE RW,0 Ebox Big Endian mode enable 3787997Ssaidi@eecs.umich.edu** <3> 1 DBG0 RW,0 Debug Test Select 3797997Ssaidi@eecs.umich.edu** <2:1> 2 SP RW,0 Superpage mode enable 3807997Ssaidi@eecs.umich.edu** <0> 1 M_BE RW,0 Mbox Big Endian mode enable 3817997Ssaidi@eecs.umich.edu** 3827997Ssaidi@eecs.umich.edu*/ 3837997Ssaidi@eecs.umich.edu 3847997Ssaidi@eecs.umich.edu#define MCSR_V_DBG1 5 3857997Ssaidi@eecs.umich.edu#define MCSR_M_DBG1 (1<<MCSR_V_DBG1) 3867997Ssaidi@eecs.umich.edu#define MCSR_V_E_BE 4 3877997Ssaidi@eecs.umich.edu#define MCSR_M_E_BE (1<<MCSR_V_E_BE) 3887997Ssaidi@eecs.umich.edu#define MCSR_V_DBG0 3 3897997Ssaidi@eecs.umich.edu#define MCSR_M_DBG0 (1<<MCSR_V_DBG0) 3907997Ssaidi@eecs.umich.edu#define MCSR_V_SP 1 3917997Ssaidi@eecs.umich.edu#define MCSR_M_SP (3<<MCSR_V_SP) 3927997Ssaidi@eecs.umich.edu#define MCSR_V_M_BE 0 3937997Ssaidi@eecs.umich.edu#define MCSR_M_M_BE (1<<MCSR_V_M_BE) 3947997Ssaidi@eecs.umich.edu 3957997Ssaidi@eecs.umich.edu/* 3967997Ssaidi@eecs.umich.edu** 3977997Ssaidi@eecs.umich.edu** Dcache Parity Error Status Register (DCPERR) Bit Summary 3987997Ssaidi@eecs.umich.edu** 3997997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 4007997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- ------------------------------------ 4017997Ssaidi@eecs.umich.edu** <5> 1 TP1 RO Dcache bank 1 tag parity error 4027997Ssaidi@eecs.umich.edu** <4> 1 TP0 RO Dcache bank 0 tag parity error 4037997Ssaidi@eecs.umich.edu** <3> 1 DP1 RO Dcache bank 1 data parity error 4047997Ssaidi@eecs.umich.edu** <2> 1 DP0 RO Dcache bank 0 data parity error 4057997Ssaidi@eecs.umich.edu** <1> 1 LOCK W1C Locks/clears bits <5:2> 4067997Ssaidi@eecs.umich.edu** <0> 1 SEO W1C Second Dcache parity error occurred 4077997Ssaidi@eecs.umich.edu** 4087997Ssaidi@eecs.umich.edu*/ 4097997Ssaidi@eecs.umich.edu 4107997Ssaidi@eecs.umich.edu#define DCPERR_V_TP1 5 4117997Ssaidi@eecs.umich.edu#define DCPERR_M_TP1 (1<<DCPERR_V_TP1) 4127997Ssaidi@eecs.umich.edu#define DCPERR_V_TP0 4 4137997Ssaidi@eecs.umich.edu#define DCPERR_M_TP0 (1<<DCPERR_V_TP0) 4147997Ssaidi@eecs.umich.edu#define DCPERR_V_DP1 3 4157997Ssaidi@eecs.umich.edu#define DCPERR_M_DP1 (1<<DCPERR_V_DP1) 4167997Ssaidi@eecs.umich.edu#define DCPERR_V_DP0 2 4177997Ssaidi@eecs.umich.edu#define DCPERR_M_DP0 (1<<DCPERR_V_DP0) 4187997Ssaidi@eecs.umich.edu#define DCPERR_V_LOCK 1 4197997Ssaidi@eecs.umich.edu#define DCPERR_M_LOCK (1<<DCPERR_V_LOCK) 4207997Ssaidi@eecs.umich.edu#define DCPERR_V_SEO 0 4217997Ssaidi@eecs.umich.edu#define DCPERR_M_SEO (1<<DCPERR_V_SEO) 4227997Ssaidi@eecs.umich.edu 4237997Ssaidi@eecs.umich.edu#define DCPERR_M_ALL (DCPERR_M_LOCK | DCPERR_M_SEO) 4247997Ssaidi@eecs.umich.edu 4257997Ssaidi@eecs.umich.edu/* 4267997Ssaidi@eecs.umich.edu** 4277997Ssaidi@eecs.umich.edu** Dcache Mode Register (DC_MODE) Bit Summary 4287997Ssaidi@eecs.umich.edu** 4297997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 4307997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- --------------------------------- 4317997Ssaidi@eecs.umich.edu** <4> 1 DOA RO Hardware Dcache Disable 4327997Ssaidi@eecs.umich.edu** <3> 1 PERR_DIS RW,0 Disable Dcache Parity Error reporting 4337997Ssaidi@eecs.umich.edu** <2> 1 BAD_DP RW,0 Force Dcache data bad parity 4347997Ssaidi@eecs.umich.edu** <1> 1 FHIT RW,0 Force Dcache hit 4357997Ssaidi@eecs.umich.edu** <0> 1 ENA RW,0 Software Dcache Enable 4367997Ssaidi@eecs.umich.edu** 4377997Ssaidi@eecs.umich.edu*/ 4387997Ssaidi@eecs.umich.edu 4397997Ssaidi@eecs.umich.edu#define DC_V_DOA 4 4407997Ssaidi@eecs.umich.edu#define DC_M_DOA (1<<DC_V_DOA) 4417997Ssaidi@eecs.umich.edu#define DC_V_PERR_DIS 3 4427997Ssaidi@eecs.umich.edu#define DC_M_PERR_DIS (1<<DC_V_PERR_DIS) 4437997Ssaidi@eecs.umich.edu#define DC_V_BAD_DP 2 4447997Ssaidi@eecs.umich.edu#define DC_M_BAD_DP (1<<DC_V_BAD_DP) 4457997Ssaidi@eecs.umich.edu#define DC_V_FHIT 1 4467997Ssaidi@eecs.umich.edu#define DC_M_FHIT (1<<DC_V_FHIT) 4477997Ssaidi@eecs.umich.edu#define DC_V_ENA 0 4487997Ssaidi@eecs.umich.edu#define DC_M_ENA (1<<DC_V_ENA) 4497997Ssaidi@eecs.umich.edu 4507997Ssaidi@eecs.umich.edu/* 4517997Ssaidi@eecs.umich.edu** 4527997Ssaidi@eecs.umich.edu** Miss Address File Mode Register (MAF_MODE) Bit Summay 4537997Ssaidi@eecs.umich.edu** 4547997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 4557997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- --------------------------------- 4567997Ssaidi@eecs.umich.edu** <7> 1 WB RO,0 If set, pending WB request 4577997Ssaidi@eecs.umich.edu** <6> 1 DREAD RO,0 If set, pending D-read request 4587997Ssaidi@eecs.umich.edu** 4597997Ssaidi@eecs.umich.edu*/ 4607997Ssaidi@eecs.umich.edu 4617997Ssaidi@eecs.umich.edu#define MAF_V_WB_PENDING 7 4627997Ssaidi@eecs.umich.edu#define MAF_M_WB_PENDING (1<<MAF_V_WB_PENDING) 4637997Ssaidi@eecs.umich.edu#define MAF_V_DREAD_PENDING 6 4647997Ssaidi@eecs.umich.edu#define MAF_M_DREAD_PENDING (1<<MAF_V_DREAD_PENDING) 4657997Ssaidi@eecs.umich.edu 4667997Ssaidi@eecs.umich.edu/* 4677997Ssaidi@eecs.umich.edu** 4687997Ssaidi@eecs.umich.edu** Cbox IPR Definitions: 4697997Ssaidi@eecs.umich.edu** 4707997Ssaidi@eecs.umich.edu*/ 4717997Ssaidi@eecs.umich.edu 4727997Ssaidi@eecs.umich.edu#define scCtl 0x0A8 /* RW - Scache Control */ 4737997Ssaidi@eecs.umich.edu#define scStat 0x0E8 /* RO - Scache Error Status */ 4747997Ssaidi@eecs.umich.edu#define scAddr 0x188 /* RO - Scache Error Address */ 4757997Ssaidi@eecs.umich.edu#define bcCtl 0x128 /* WO - Bcache/System Interface Control */ 4767997Ssaidi@eecs.umich.edu#define bcCfg 0x1C8 /* WO - Bcache Configuration Parameters */ 4777997Ssaidi@eecs.umich.edu#define bcTagAddr 0x108 /* RO - Bcache Tag */ 4787997Ssaidi@eecs.umich.edu#define eiStat 0x168 /* RO - Bcache/System Error Status */ 4797997Ssaidi@eecs.umich.edu#define eiAddr 0x148 /* RO - Bcache/System Error Address */ 4807997Ssaidi@eecs.umich.edu#define fillSyn 0x068 /* RO - Fill Syndrome */ 4817997Ssaidi@eecs.umich.edu#define ldLock 0x1E8 /* RO - LDx_L Address */ 4827997Ssaidi@eecs.umich.edu 4837997Ssaidi@eecs.umich.edu/* 4847997Ssaidi@eecs.umich.edu** 4857997Ssaidi@eecs.umich.edu** Scache Control Register (SC_CTL) Bit Summary 4867997Ssaidi@eecs.umich.edu** 4877997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 4887997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- --------------------------------- 4897997Ssaidi@eecs.umich.edu** <15:13> 3 SET_EN RW,1 Set enable 4907997Ssaidi@eecs.umich.edu** <12> 1 BLK_SIZE RW,1 Scache/Bcache block size select 4917997Ssaidi@eecs.umich.edu** <11:08> 4 FB_DP RW,0 Force bad data parity 4927997Ssaidi@eecs.umich.edu** <07:02> 6 TAG_STAT RW Tag status and parity 4937997Ssaidi@eecs.umich.edu** <1> 1 FLUSH RW,0 If set, clear all tag valid bits 4947997Ssaidi@eecs.umich.edu** <0> 1 FHIT RW,0 Force hits 4957997Ssaidi@eecs.umich.edu** 4967997Ssaidi@eecs.umich.edu*/ 4977997Ssaidi@eecs.umich.edu 4987997Ssaidi@eecs.umich.edu#define SC_V_SET_EN 13 4997997Ssaidi@eecs.umich.edu#define SC_M_SET_EN (7<<SC_V_SET_EN) 5007997Ssaidi@eecs.umich.edu#define SC_V_BLK_SIZE 12 5017997Ssaidi@eecs.umich.edu#define SC_M_BLK_SIZE (1<<SC_V_BLK_SIZE) 5027997Ssaidi@eecs.umich.edu#define SC_V_FB_DP 8 5037997Ssaidi@eecs.umich.edu#define SC_M_FB_DP (0xF<<SC_V_FB_DP) 5047997Ssaidi@eecs.umich.edu#define SC_V_TAG_STAT 2 5057997Ssaidi@eecs.umich.edu#define SC_M_TAG_STAT (0x3F<<SC_V_TAG_STAT) 5067997Ssaidi@eecs.umich.edu#define SC_V_FLUSH 1 5077997Ssaidi@eecs.umich.edu#define SC_M_FLUSH (1<<SC_V_FLUSH) 5087997Ssaidi@eecs.umich.edu#define SC_V_FHIT 0 5097997Ssaidi@eecs.umich.edu#define SC_M_FHIT (1<<SC_V_FHIT) 5107997Ssaidi@eecs.umich.edu 5117997Ssaidi@eecs.umich.edu/* 5127997Ssaidi@eecs.umich.edu** 5137997Ssaidi@eecs.umich.edu** Bcache Control Register (BC_CTL) Bit Summary 5147997Ssaidi@eecs.umich.edu** 5157997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 5167997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- --------------------------------- 5177997Ssaidi@eecs.umich.edu** <27> 1 DIS_VIC_BUF WO,0 Disable Scache victim buffer 5187997Ssaidi@eecs.umich.edu** <26> 1 DIS_BAF_BYP WO,0 Disable speculative Bcache reads 5197997Ssaidi@eecs.umich.edu** <25> 1 DBG_MUX_SEL WO,0 Debug MUX select 5207997Ssaidi@eecs.umich.edu** <24:19> 6 PM_MUX_SEL WO,0 Performance counter MUX select 5217997Ssaidi@eecs.umich.edu** <18:17> 2 BC_WAVE WO,0 Number of cycles of wave pipelining 5227997Ssaidi@eecs.umich.edu** <16> 1 TL_PIPE_LATCH WO,0 Pipe system control pins 5237997Ssaidi@eecs.umich.edu** <15> 1 EI_DIS_ERR WO,1 Disable ECC (parity) error 5247997Ssaidi@eecs.umich.edu** <14:13> 2 BC_BAD_DAT WO,0 Force bad data 5257997Ssaidi@eecs.umich.edu** <12:08> 5 BC_TAG_STAT WO Bcache tag status and parity 5267997Ssaidi@eecs.umich.edu** <7> 1 BC_FHIT WO,0 Bcache force hit 5277997Ssaidi@eecs.umich.edu** <6> 1 EI_ECC WO,1 ECC or byte parity mode 5287997Ssaidi@eecs.umich.edu** <5> 1 VTM_FIRST WO,1 Drive out victim block address first 5297997Ssaidi@eecs.umich.edu** <4> 1 CORR_FILL_DAT WO,1 Correct fill data 5307997Ssaidi@eecs.umich.edu** <3> 1 EI_CMD_GRP3 WO,0 Drive MB command to external pins 5317997Ssaidi@eecs.umich.edu** <2> 1 EI_CMD_GRP2 WO,0 Drive LOCK & SET_DIRTY to ext. pins 5327997Ssaidi@eecs.umich.edu** <1> 1 ALLOC_CYC WO,0 Allocate cycle for non-cached LDs. 5337997Ssaidi@eecs.umich.edu** <0> 1 BC_ENA W0,0 Bcache enable 5347997Ssaidi@eecs.umich.edu** 5357997Ssaidi@eecs.umich.edu*/ 5367997Ssaidi@eecs.umich.edu#define BC_V_DIS_SC_VIC_BUF 27 5377997Ssaidi@eecs.umich.edu#define BC_M_DIS_SC_VIC_BUF (1<<BC_V_DIS_SC_VIC_BUF) 5387997Ssaidi@eecs.umich.edu#define BC_V_DIS_BAF_BYP 26 5397997Ssaidi@eecs.umich.edu#define BC_M_DIS_BAF_BYP (1<<BC_V_DIS_BAF_BYP) 5407997Ssaidi@eecs.umich.edu#define BC_V_DBG_MUX_SEL 25 5417997Ssaidi@eecs.umich.edu#define BC_M_DBG_MUX_SEL (1<<BC_V_DBG_MUX_SEL) 5427997Ssaidi@eecs.umich.edu#define BC_V_PM_MUX_SEL 19 5437997Ssaidi@eecs.umich.edu#define BC_M_PM_MUX_SEL (0x3F<<BC_V_PM_MUX_SEL) 5447997Ssaidi@eecs.umich.edu#define BC_V_BC_WAVE 17 5457997Ssaidi@eecs.umich.edu#define BC_M_BC_WAVE (3<<BC_V_BC_WAVE) 5467997Ssaidi@eecs.umich.edu#define BC_V_TL_PIPE_LATCH 16 5477997Ssaidi@eecs.umich.edu#define BC_M_TL_PIPE_LATCH (1<<BC_V_TL_PIPE_LATCH) 5487997Ssaidi@eecs.umich.edu#define BC_V_EI_DIS_ERR 15 5497997Ssaidi@eecs.umich.edu#define BC_M_EI_DIS_ERR (1<<BC_V_EI_DIS_ERR) 5507997Ssaidi@eecs.umich.edu#define BC_V_BC_BAD_DAT 13 5517997Ssaidi@eecs.umich.edu#define BC_M_BC_BAD_DAT (3<<BC_V_BC_BAD_DAT) 5527997Ssaidi@eecs.umich.edu#define BC_V_BC_TAG_STAT 8 5537997Ssaidi@eecs.umich.edu#define BC_M_BC_TAG_STAT (0x1F<<BC_V_BC_TAG_STAT) 5547997Ssaidi@eecs.umich.edu#define BC_V_BC_FHIT 7 5557997Ssaidi@eecs.umich.edu#define BC_M_BC_FHIT (1<<BC_V_BC_FHIT) 5567997Ssaidi@eecs.umich.edu#define BC_V_EI_ECC_OR_PARITY 6 5577997Ssaidi@eecs.umich.edu#define BC_M_EI_ECC_OR_PARITY (1<<BC_V_EI_ECC_OR_PARITY) 5587997Ssaidi@eecs.umich.edu#define BC_V_VTM_FIRST 5 5597997Ssaidi@eecs.umich.edu#define BC_M_VTM_FIRST (1<<BC_V_VTM_FIRST) 5607997Ssaidi@eecs.umich.edu#define BC_V_CORR_FILL_DAT 4 5617997Ssaidi@eecs.umich.edu#define BC_M_CORR_FILL_DAT (1<<BC_V_CORR_FILL_DAT) 5627997Ssaidi@eecs.umich.edu#define BC_V_EI_CMD_GRP3 3 5637997Ssaidi@eecs.umich.edu#define BC_M_EI_CMD_GRP3 (1<<BC_V_EI_CMD_GRP3) 5647997Ssaidi@eecs.umich.edu#define BC_V_EI_CMD_GRP2 2 5657997Ssaidi@eecs.umich.edu#define BC_M_EI_CMD_GRP2 (1<<BC_V_EI_CMD_GRP2) 5667997Ssaidi@eecs.umich.edu#define BC_V_ALLOC_CYC 1 5677997Ssaidi@eecs.umich.edu#define BC_M_ALLOC_CYC (1<<BC_V_ALLOC_CYC) 5687997Ssaidi@eecs.umich.edu#define BC_V_BC_ENA 0 5697997Ssaidi@eecs.umich.edu#define BC_M_BC_ENA (1<<BC_V_BC_ENA) 5707997Ssaidi@eecs.umich.edu 5717997Ssaidi@eecs.umich.edu#define BC_K_DFAULT \ 5727997Ssaidi@eecs.umich.edu (((BC_M_EI_DIS_ERR) | \ 5737997Ssaidi@eecs.umich.edu (BC_M_EI_ECC_OR_PARITY) | \ 5747997Ssaidi@eecs.umich.edu (BC_M_VTM_FIRST) | \ 5757997Ssaidi@eecs.umich.edu (BC_M_CORR_FILL_DAT))>>1) 5767997Ssaidi@eecs.umich.edu/* 5777997Ssaidi@eecs.umich.edu** 5787997Ssaidi@eecs.umich.edu** Bcache Configuration Register (BC_CONFIG) Bit Summary 5797997Ssaidi@eecs.umich.edu** 5807997Ssaidi@eecs.umich.edu** Extent Size Name Type Function 5817997Ssaidi@eecs.umich.edu** ------ ---- ---- ---- --------------------------------- 5827997Ssaidi@eecs.umich.edu** <35:29> 7 RSVD WO Reserved - Must Be Zero 5837997Ssaidi@eecs.umich.edu** <28:20> 9 WE_CTL WO,0 Bcache write enable control 5847997Ssaidi@eecs.umich.edu** <19:19> 1 RSVD WO,0 Reserved - Must Be Zero 5857997Ssaidi@eecs.umich.edu** <18:16> 3 WE_OFF WO,1 Bcache fill write enable pulse offset 5867997Ssaidi@eecs.umich.edu** <15:15> 1 RSVD WO,0 Reserved - Must Be Zero 5877997Ssaidi@eecs.umich.edu** <14:12> 3 RD_WR_SPC WO,7 Bcache private read/write spacing 5887997Ssaidi@eecs.umich.edu** <11:08> 4 WR_SPD WO,4 Bcache write speed in CPU cycles 5897997Ssaidi@eecs.umich.edu** <07:04> 4 RD_SPD WO,4 Bcache read speed in CPU cycles 5907997Ssaidi@eecs.umich.edu** <03:03> 1 RSVD WO,0 Reserved - Must Be Zero 5917997Ssaidi@eecs.umich.edu** <02:00> 3 SIZE WO,1 Bcache size 5927997Ssaidi@eecs.umich.edu*/ 5937997Ssaidi@eecs.umich.edu#define BC_V_WE_CTL 20 5947997Ssaidi@eecs.umich.edu#define BC_M_WE_CTL (0x1FF<<BC_V_WE_CTL) 5957997Ssaidi@eecs.umich.edu#define BC_V_WE_OFF 16 5967997Ssaidi@eecs.umich.edu#define BC_M_WE_OFF (0x7<<BC_V_WE_OFF) 5977997Ssaidi@eecs.umich.edu#define BC_V_RD_WR_SPC 12 5987997Ssaidi@eecs.umich.edu#define BC_M_RD_WR_SPC (0x7<<BC_V_RD_WR_SPC) 5997997Ssaidi@eecs.umich.edu#define BC_V_WR_SPD 8 6007997Ssaidi@eecs.umich.edu#define BC_M_WR_SPD (0xF<<BC_V_WR_SPD) 6017997Ssaidi@eecs.umich.edu#define BC_V_RD_SPD 4 6027997Ssaidi@eecs.umich.edu#define BC_M_RD_SPD (0xF<<BC_V_RD_SPD) 6037997Ssaidi@eecs.umich.edu#define BC_V_SIZE 0 6047997Ssaidi@eecs.umich.edu#define BC_M_SIZE (0x7<<BC_V_SIZE) 6057997Ssaidi@eecs.umich.edu 6067997Ssaidi@eecs.umich.edu#define BC_K_CONFIG \ 6077997Ssaidi@eecs.umich.edu ((0x1<<BC_V_WE_OFF) | \ 6087997Ssaidi@eecs.umich.edu (0x7<<BC_V_RD_WR_SPC) | \ 6097997Ssaidi@eecs.umich.edu (0x4<<BC_V_WR_SPD) | \ 6107997Ssaidi@eecs.umich.edu (0x4<<BC_V_RD_SPD) | \ 6117997Ssaidi@eecs.umich.edu (0x1<<BC_V_SIZE)) 6127997Ssaidi@eecs.umich.edu 6137997Ssaidi@eecs.umich.edu/* 6147997Ssaidi@eecs.umich.edu** 6157997Ssaidi@eecs.umich.edu** DECchip 21164 Privileged Architecture Library Entry Offsets: 6167997Ssaidi@eecs.umich.edu** 6177997Ssaidi@eecs.umich.edu** Entry Name Offset (Hex) 6187997Ssaidi@eecs.umich.edu** 6197997Ssaidi@eecs.umich.edu** RESET 0000 6207997Ssaidi@eecs.umich.edu** IACCVIO 0080 6217997Ssaidi@eecs.umich.edu** INTERRUPT 0100 6227997Ssaidi@eecs.umich.edu** ITB_MISS 0180 6237997Ssaidi@eecs.umich.edu** DTB_MISS (Single) 0200 6247997Ssaidi@eecs.umich.edu** DTB_MISS (Double) 0280 6257997Ssaidi@eecs.umich.edu** UNALIGN 0300 6267997Ssaidi@eecs.umich.edu** D_FAULT 0380 6277997Ssaidi@eecs.umich.edu** MCHK 0400 6287997Ssaidi@eecs.umich.edu** OPCDEC 0480 6297997Ssaidi@eecs.umich.edu** ARITH 0500 6307997Ssaidi@eecs.umich.edu** FEN 0580 6317997Ssaidi@eecs.umich.edu** CALL_PAL (Privileged) 2000 6327997Ssaidi@eecs.umich.edu** CALL_PAL (Unprivileged) 3000 6337997Ssaidi@eecs.umich.edu** 6347997Ssaidi@eecs.umich.edu*/ 6357997Ssaidi@eecs.umich.edu 6367997Ssaidi@eecs.umich.edu#define PAL_RESET_ENTRY 0x0000 6377997Ssaidi@eecs.umich.edu#define PAL_IACCVIO_ENTRY 0x0080 6387997Ssaidi@eecs.umich.edu#define PAL_INTERRUPT_ENTRY 0x0100 6397997Ssaidi@eecs.umich.edu#define PAL_ITB_MISS_ENTRY 0x0180 6407997Ssaidi@eecs.umich.edu#define PAL_DTB_MISS_ENTRY 0x0200 6417997Ssaidi@eecs.umich.edu#define PAL_DOUBLE_MISS_ENTRY 0x0280 6427997Ssaidi@eecs.umich.edu#define PAL_UNALIGN_ENTRY 0x0300 6437997Ssaidi@eecs.umich.edu#define PAL_D_FAULT_ENTRY 0x0380 6447997Ssaidi@eecs.umich.edu#define PAL_MCHK_ENTRY 0x0400 6457997Ssaidi@eecs.umich.edu#define PAL_OPCDEC_ENTRY 0x0480 6467997Ssaidi@eecs.umich.edu#define PAL_ARITH_ENTRY 0x0500 6477997Ssaidi@eecs.umich.edu#define PAL_FEN_ENTRY 0x0580 6487997Ssaidi@eecs.umich.edu#define PAL_CALL_PAL_PRIV_ENTRY 0x2000 6497997Ssaidi@eecs.umich.edu#define PAL_CALL_PAL_UNPRIV_ENTRY 0x3000 6507997Ssaidi@eecs.umich.edu 6517997Ssaidi@eecs.umich.edu/* 6527997Ssaidi@eecs.umich.edu** 6537997Ssaidi@eecs.umich.edu** Architecturally Reserved Opcode (PALRES) Definitions: 6547997Ssaidi@eecs.umich.edu** 6557997Ssaidi@eecs.umich.edu*/ 6567997Ssaidi@eecs.umich.edu 6577997Ssaidi@eecs.umich.edu#define mtpr hw_mtpr 6587997Ssaidi@eecs.umich.edu#define mfpr hw_mfpr 6597997Ssaidi@eecs.umich.edu 6607997Ssaidi@eecs.umich.edu#define ldl_a hw_ldl/a 6617997Ssaidi@eecs.umich.edu#define ldq_a hw_ldq/a 6627997Ssaidi@eecs.umich.edu#define stq_a hw_stq/a 6637997Ssaidi@eecs.umich.edu#define stl_a hw_stl/a 6647997Ssaidi@eecs.umich.edu 6657997Ssaidi@eecs.umich.edu#define ldl_p hw_ldl/p 6667997Ssaidi@eecs.umich.edu#define ldq_p hw_ldq/p 6677997Ssaidi@eecs.umich.edu#define stl_p hw_stl/p 6687997Ssaidi@eecs.umich.edu#define stq_p hw_stq/p 6697997Ssaidi@eecs.umich.edu 6707997Ssaidi@eecs.umich.edu/* 6717997Ssaidi@eecs.umich.edu** Virtual PTE fetch variants of HW_LD. 6727997Ssaidi@eecs.umich.edu*/ 6737997Ssaidi@eecs.umich.edu#define ld_vpte hw_ldq/v 6747997Ssaidi@eecs.umich.edu 6757997Ssaidi@eecs.umich.edu/* 6767997Ssaidi@eecs.umich.edu** Physical mode load-lock and store-conditional variants of 6777997Ssaidi@eecs.umich.edu** HW_LD and HW_ST. 6787997Ssaidi@eecs.umich.edu*/ 6797997Ssaidi@eecs.umich.edu 6807997Ssaidi@eecs.umich.edu#define ldq_lp hw_ldq/pl 6817997Ssaidi@eecs.umich.edu#define stq_cp hw_stq/pc 6827997Ssaidi@eecs.umich.edu 6837997Ssaidi@eecs.umich.edu/* 6847997Ssaidi@eecs.umich.edu** 6857997Ssaidi@eecs.umich.edu** General Purpose Register Definitions: 6867997Ssaidi@eecs.umich.edu** 6877997Ssaidi@eecs.umich.edu*/ 6887997Ssaidi@eecs.umich.edu 6897997Ssaidi@eecs.umich.edu#define r0 $0 6907997Ssaidi@eecs.umich.edu#define r1 $1 6917997Ssaidi@eecs.umich.edu#define r2 $2 6927997Ssaidi@eecs.umich.edu#define r3 $3 6937997Ssaidi@eecs.umich.edu#define r4 $4 6947997Ssaidi@eecs.umich.edu#define r5 $5 6957997Ssaidi@eecs.umich.edu#define r6 $6 6967997Ssaidi@eecs.umich.edu#define r7 $7 6977997Ssaidi@eecs.umich.edu#define r8 $8 6987997Ssaidi@eecs.umich.edu#define r9 $9 6997997Ssaidi@eecs.umich.edu#define r10 $10 7007997Ssaidi@eecs.umich.edu#define r11 $11 7017997Ssaidi@eecs.umich.edu#define r12 $12 7027997Ssaidi@eecs.umich.edu#define r13 $13 7037997Ssaidi@eecs.umich.edu#define r14 $14 7047997Ssaidi@eecs.umich.edu#define r15 $15 7057997Ssaidi@eecs.umich.edu#define r16 $16 7067997Ssaidi@eecs.umich.edu#define r17 $17 7077997Ssaidi@eecs.umich.edu#define r18 $18 7087997Ssaidi@eecs.umich.edu#define r19 $19 7097997Ssaidi@eecs.umich.edu#define r20 $20 7107997Ssaidi@eecs.umich.edu#define r21 $21 7117997Ssaidi@eecs.umich.edu#define r22 $22 7127997Ssaidi@eecs.umich.edu#define r23 $23 7137997Ssaidi@eecs.umich.edu#define r24 $24 7147997Ssaidi@eecs.umich.edu#define r25 $25 7157997Ssaidi@eecs.umich.edu#define r26 $26 7167997Ssaidi@eecs.umich.edu#define r27 $27 7177997Ssaidi@eecs.umich.edu#define r28 $28 7187997Ssaidi@eecs.umich.edu#define r29 $29 7197997Ssaidi@eecs.umich.edu#define r30 $30 7207997Ssaidi@eecs.umich.edu#define r31 $31 7217997Ssaidi@eecs.umich.edu 7227997Ssaidi@eecs.umich.edu/* 7237997Ssaidi@eecs.umich.edu** 7247997Ssaidi@eecs.umich.edu** Floating Point Register Definitions: 7257997Ssaidi@eecs.umich.edu** 7267997Ssaidi@eecs.umich.edu*/ 7277997Ssaidi@eecs.umich.edu 7287997Ssaidi@eecs.umich.edu#define f0 $f0 7297997Ssaidi@eecs.umich.edu#define f1 $f1 7307997Ssaidi@eecs.umich.edu#define f2 $f2 7317997Ssaidi@eecs.umich.edu#define f3 $f3 7327997Ssaidi@eecs.umich.edu#define f4 $f4 7337997Ssaidi@eecs.umich.edu#define f5 $f5 7347997Ssaidi@eecs.umich.edu#define f6 $f6 7357997Ssaidi@eecs.umich.edu#define f7 $f7 7367997Ssaidi@eecs.umich.edu#define f8 $f8 7377997Ssaidi@eecs.umich.edu#define f9 $f9 7387997Ssaidi@eecs.umich.edu#define f10 $f10 7397997Ssaidi@eecs.umich.edu#define f11 $f11 7407997Ssaidi@eecs.umich.edu#define f12 $f12 7417997Ssaidi@eecs.umich.edu#define f13 $f13 7427997Ssaidi@eecs.umich.edu#define f14 $f14 7437997Ssaidi@eecs.umich.edu#define f15 $f15 7447997Ssaidi@eecs.umich.edu#define f16 $f16 7457997Ssaidi@eecs.umich.edu#define f17 $f17 7467997Ssaidi@eecs.umich.edu#define f18 $f18 7477997Ssaidi@eecs.umich.edu#define f19 $f19 7487997Ssaidi@eecs.umich.edu#define f20 $f20 7497997Ssaidi@eecs.umich.edu#define f21 $f21 7507997Ssaidi@eecs.umich.edu#define f22 $f22 7517997Ssaidi@eecs.umich.edu#define f23 $f23 7527997Ssaidi@eecs.umich.edu#define f24 $f24 7537997Ssaidi@eecs.umich.edu#define f25 $f25 7547997Ssaidi@eecs.umich.edu#define f26 $f26 7557997Ssaidi@eecs.umich.edu#define f27 $f27 7567997Ssaidi@eecs.umich.edu#define f28 $f28 7577997Ssaidi@eecs.umich.edu#define f29 $f29 7587997Ssaidi@eecs.umich.edu#define f30 $f30 7597997Ssaidi@eecs.umich.edu#define f31 $f31 7607997Ssaidi@eecs.umich.edu 7617997Ssaidi@eecs.umich.edu/* 7627997Ssaidi@eecs.umich.edu** 7637997Ssaidi@eecs.umich.edu** PAL Temporary Register Definitions: 7647997Ssaidi@eecs.umich.edu** 7657997Ssaidi@eecs.umich.edu*/ 7667997Ssaidi@eecs.umich.edu 7677997Ssaidi@eecs.umich.edu// covered by fetch distribution..pb Nov/95 7687997Ssaidi@eecs.umich.edu 7697997Ssaidi@eecs.umich.edu// #define pt0 0x140 7707997Ssaidi@eecs.umich.edu// #define pt1 0x141 7717997Ssaidi@eecs.umich.edu// #define pt2 0x142 7727997Ssaidi@eecs.umich.edu// #define pt3 0x143 7737997Ssaidi@eecs.umich.edu// #define pt4 0x144 7747997Ssaidi@eecs.umich.edu// #define pt5 0x145 7757997Ssaidi@eecs.umich.edu// #define pt6 0x146 7767997Ssaidi@eecs.umich.edu// #define pt7 0x147 7777997Ssaidi@eecs.umich.edu// #define pt8 0x148 7787997Ssaidi@eecs.umich.edu// #define pt9 0x149 7797997Ssaidi@eecs.umich.edu// #define pt10 0x14A 7807997Ssaidi@eecs.umich.edu// #define pt11 0x14B 7817997Ssaidi@eecs.umich.edu// #define pt12 0x14C 7827997Ssaidi@eecs.umich.edu// #define pt13 0x14D 7837997Ssaidi@eecs.umich.edu// #define pt14 0x14E 7847997Ssaidi@eecs.umich.edu// #define pt15 0x14F 7857997Ssaidi@eecs.umich.edu// #define pt16 0x150 7867997Ssaidi@eecs.umich.edu// #define pt17 0x151 7877997Ssaidi@eecs.umich.edu// #define pt18 0x152 7887997Ssaidi@eecs.umich.edu// #define pt19 0x153 7897997Ssaidi@eecs.umich.edu// #define pt20 0x154 7907997Ssaidi@eecs.umich.edu// #define pt21 0x155 7917997Ssaidi@eecs.umich.edu// #define pt22 0x156 7927997Ssaidi@eecs.umich.edu// #define pt23 0x157 7937997Ssaidi@eecs.umich.edu 7947997Ssaidi@eecs.umich.edu/* 7957997Ssaidi@eecs.umich.edu** PAL Shadow Registers: 7967997Ssaidi@eecs.umich.edu** 7977997Ssaidi@eecs.umich.edu** The DECchip 21164 shadows r8-r14 and r25 when in PALmode and 7987997Ssaidi@eecs.umich.edu** ICSR<SDE> = 1. 7997997Ssaidi@eecs.umich.edu*/ 8007997Ssaidi@eecs.umich.edu 8017997Ssaidi@eecs.umich.edu#define p0 r8 /* ITB/DTB Miss Scratch */ 8027997Ssaidi@eecs.umich.edu#define p1 r9 /* ITB/DTB Miss Scratch */ 8037997Ssaidi@eecs.umich.edu#define p2 r10 /* ITB/DTB Miss Scratch */ 8047997Ssaidi@eecs.umich.edu#define p3 r11 8057997Ssaidi@eecs.umich.edu// #define ps r11 /* Processor Status */ 8067997Ssaidi@eecs.umich.edu#define p4 r12 /* Local Scratch */ 8077997Ssaidi@eecs.umich.edu#define p5 r13 /* Local Scratch */ 8087997Ssaidi@eecs.umich.edu#define p6 r14 /* Local Scratch */ 8097997Ssaidi@eecs.umich.edu#define p7 r25 /* Local Scratch */ 8107997Ssaidi@eecs.umich.edu 8117997Ssaidi@eecs.umich.edu/* 8127997Ssaidi@eecs.umich.edu** SRM Defined State Definitions: 8137997Ssaidi@eecs.umich.edu*/ 8147997Ssaidi@eecs.umich.edu 8157997Ssaidi@eecs.umich.edu/* 8167997Ssaidi@eecs.umich.edu** This table is an accounting of the DECchip 21164 storage used to 8177997Ssaidi@eecs.umich.edu** implement the SRM defined state for OSF/1. 8187997Ssaidi@eecs.umich.edu** 8197997Ssaidi@eecs.umich.edu** IPR Name Internal Storage 8207997Ssaidi@eecs.umich.edu** -------- ---------------- 8217997Ssaidi@eecs.umich.edu** Processor Status ps, dtbCm, ipl, r11 8227997Ssaidi@eecs.umich.edu** Program Counter Ibox 8237997Ssaidi@eecs.umich.edu** Interrupt Entry ptEntInt 8247997Ssaidi@eecs.umich.edu** Arith Trap Entry ptEntArith 8257997Ssaidi@eecs.umich.edu** MM Fault Entry ptEntMM 8267997Ssaidi@eecs.umich.edu** Unaligned Access Entry ptEntUna 8277997Ssaidi@eecs.umich.edu** Instruction Fault Entry ptEntIF 8287997Ssaidi@eecs.umich.edu** Call System Entry ptEntSys 8297997Ssaidi@eecs.umich.edu** User Stack Pointer ptUsp 8307997Ssaidi@eecs.umich.edu** Kernel Stack Pointer ptKsp 8317997Ssaidi@eecs.umich.edu** Kernel Global Pointer ptKgp 8327997Ssaidi@eecs.umich.edu** System Value ptSysVal 8337997Ssaidi@eecs.umich.edu** Page Table Base Register ptPtbr 8347997Ssaidi@eecs.umich.edu** Virtual Page Table Base iVptBr, mVptBr 8357997Ssaidi@eecs.umich.edu** Process Control Block Base ptPcbb 8367997Ssaidi@eecs.umich.edu** Address Space Number itbAsn, dtbAsn 8377997Ssaidi@eecs.umich.edu** Cycle Counter cc, ccCtl 8387997Ssaidi@eecs.umich.edu** Float Point Enable icsr 8397997Ssaidi@eecs.umich.edu** Lock Flag Cbox/System 8407997Ssaidi@eecs.umich.edu** Unique PCB 8417997Ssaidi@eecs.umich.edu** Who-Am-I ptWhami 8427997Ssaidi@eecs.umich.edu*/ 8437997Ssaidi@eecs.umich.edu 8447997Ssaidi@eecs.umich.edu#define ptEntUna pt2 /* Unaligned Access Dispatch Entry */ 8457997Ssaidi@eecs.umich.edu#define ptImpure pt3 /* Pointer To PAL Scratch Area */ 8467997Ssaidi@eecs.umich.edu#define ptEntIF pt7 /* Instruction Fault Dispatch Entry */ 8477997Ssaidi@eecs.umich.edu#define ptIntMask pt8 /* Interrupt Enable Mask */ 8487997Ssaidi@eecs.umich.edu#define ptEntSys pt9 /* Call System Dispatch Entry */ 8497997Ssaidi@eecs.umich.edu#define ptTrap pt11 8507997Ssaidi@eecs.umich.edu#define ptEntInt pt11 /* Hardware Interrupt Dispatch Entry */ 8517997Ssaidi@eecs.umich.edu#define ptEntArith pt12 /* Arithmetic Trap Dispatch Entry */ 8527997Ssaidi@eecs.umich.edu#if defined(KDEBUG) 8537997Ssaidi@eecs.umich.edu#define ptEntDbg pt13 /* Kernel Debugger Dispatch Entry */ 8547997Ssaidi@eecs.umich.edu#endif /* KDEBUG */ 8557997Ssaidi@eecs.umich.edu#define ptMisc pt16 /* Miscellaneous Flags */ 8567997Ssaidi@eecs.umich.edu#define ptWhami pt16 /* Who-Am-I Register Pt16<15:8> */ 8577997Ssaidi@eecs.umich.edu#define ptMces pt16 /* Machine Check Error Summary Pt16<4:0> */ 8587997Ssaidi@eecs.umich.edu#define ptSysVal pt17 /* Per-Processor System Value */ 8597997Ssaidi@eecs.umich.edu#define ptUsp pt18 /* User Stack Pointer */ 8607997Ssaidi@eecs.umich.edu#define ptKsp pt19 /* Kernel Stack Pointer */ 8617997Ssaidi@eecs.umich.edu#define ptPtbr pt20 /* Page Table Base Register */ 8627997Ssaidi@eecs.umich.edu#define ptEntMM pt21 /* MM Fault Dispatch Entry */ 8637997Ssaidi@eecs.umich.edu#define ptKgp pt22 /* Kernel Global Pointer */ 8647997Ssaidi@eecs.umich.edu#define ptPcbb pt23 /* Process Control Block Base */ 8657997Ssaidi@eecs.umich.edu 8667997Ssaidi@eecs.umich.edu/* 8677997Ssaidi@eecs.umich.edu** 8687997Ssaidi@eecs.umich.edu** Miscellaneous PAL State Flags (ptMisc) Bit Summary 8697997Ssaidi@eecs.umich.edu** 8707997Ssaidi@eecs.umich.edu** Extent Size Name Function 8717997Ssaidi@eecs.umich.edu** ------ ---- ---- --------------------------------- 8727997Ssaidi@eecs.umich.edu** <55:48> 8 SWAP Swap PALcode flag -- character 'S' 8737997Ssaidi@eecs.umich.edu** <47:32> 16 MCHK Machine Check Error code 8747997Ssaidi@eecs.umich.edu** <31:16> 16 SCB System Control Block vector 8757997Ssaidi@eecs.umich.edu** <15:08> 8 WHAMI Who-Am-I identifier 8767997Ssaidi@eecs.umich.edu** <04:00> 5 MCES Machine Check Error Summary bits 8777997Ssaidi@eecs.umich.edu** 8787997Ssaidi@eecs.umich.edu*/ 8797997Ssaidi@eecs.umich.edu 8807997Ssaidi@eecs.umich.edu#define PT16_V_MCES 0 8817997Ssaidi@eecs.umich.edu#define PT16_V_WHAMI 8 8827997Ssaidi@eecs.umich.edu#define PT16_V_SCB 16 8837997Ssaidi@eecs.umich.edu#define PT16_V_MCHK 32 8847997Ssaidi@eecs.umich.edu#define PT16_V_SWAP 48 8857997Ssaidi@eecs.umich.edu 8867997Ssaidi@eecs.umich.edu#endif /* DC21164FROMGASSOURCES_INCLUDED */ 887