SimpleLTTarget_ext.h revision 12855:588919e0e4aa
1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20#ifndef __SIMPLE_LT_TARGET2_H__ 21#define __SIMPLE_LT_TARGET2_H__ 22 23#include "tlm.h" 24#include "tlm_utils/simple_target_socket.h" 25#include "my_extension.h" 26 27//#include <systemc> 28#include <cassert> 29#include <vector> 30//#include <iostream> 31 32class SimpleLTTarget_ext : public sc_core::sc_module 33{ 34public: 35 typedef tlm::tlm_generic_payload transaction_type; 36 typedef tlm::tlm_phase phase_type; 37 typedef tlm::tlm_sync_enum sync_enum_type; 38 typedef tlm_utils::simple_target_socket<SimpleLTTarget_ext, 32, 39 my_extended_payload_types> target_socket_type; 40 41public: 42 target_socket_type socket; 43 44public: 45 SC_HAS_PROCESS(SimpleLTTarget_ext); 46 SimpleLTTarget_ext(sc_core::sc_module_name name, 47 sc_core::sc_time invalidate_dmi_time = sc_core::sc_time(25, sc_core::SC_NS)) : 48 sc_core::sc_module(name), 49 socket("socket") 50 { 51 // register nb_transport method 52 socket.register_nb_transport_fw(this, &SimpleLTTarget_ext::myNBTransport); 53 socket.register_get_direct_mem_ptr(this, &SimpleLTTarget_ext::myGetDMIPtr); 54 55 socket.register_transport_dbg(this, &SimpleLTTarget_ext::transport_dbg); 56 57 SC_METHOD(invalidate_dmi_method); 58 sensitive << m_invalidate_dmi_event; 59 dont_initialize(); 60 m_invalidate_dmi_time = invalidate_dmi_time; 61 } 62 63 sync_enum_type myNBTransport(transaction_type& trans, phase_type& phase, sc_core::sc_time& t) 64 { 65 sc_assert(phase == tlm::BEGIN_REQ); 66 67 my_extension* tmp_ext; 68 trans.get_extension(tmp_ext); 69 if (!tmp_ext) 70 { 71 std::cout << name() << ": ERROR, extension not present" << std::endl; 72 } 73 else 74 { 75 std::cout << name() << ": OK, extension data = " 76 << tmp_ext->m_data << std::endl; 77 } 78 sc_dt::uint64 address = trans.get_address(); 79 sc_assert(address < 400); 80 81 unsigned int& data = *reinterpret_cast<unsigned int*>(trans.get_data_ptr()); 82 if (trans.get_command() == tlm::TLM_WRITE_COMMAND) { 83 std::cout << name() << ": Received write request: A = 0x" 84 << std::hex << (unsigned int)address 85 << ", D = 0x" << data << std::dec 86 << " @ " << sc_core::sc_time_stamp() << std::endl; 87 88 *reinterpret_cast<unsigned int*>(&mMem[address]) = data; 89 t += sc_core::sc_time(10, sc_core::SC_NS); 90 91 } else { 92 std::cout << name() << ": Received read request: A = 0x" 93 << std::hex << (unsigned int)address << std::dec 94 << " @ " << sc_core::sc_time_stamp() << std::endl; 95 96 data = *reinterpret_cast<unsigned int*>(&mMem[address]); 97 t += sc_core::sc_time(100, sc_core::SC_NS); 98 } 99 100 trans.set_response_status(tlm::TLM_OK_RESPONSE); 101 102 trans.set_dmi_allowed(true); 103 104 // LT target 105 // - always return true 106 // - not necessary to update phase (if true is returned) 107 return tlm::TLM_COMPLETED; 108 } 109 110 unsigned int transport_dbg(transaction_type& r) 111 { 112 if (r.get_address() >= 400) return 0; 113 114 unsigned int tmp = (int)r.get_address(); 115 unsigned int num_bytes; 116 if (tmp + r.get_data_length() >= 400) { 117 num_bytes = 400 - tmp; 118 119 } else { 120 num_bytes = r.get_data_length(); 121 } 122 if (r.is_read()) { 123 for (unsigned int i = 0; i < num_bytes; ++i) { 124 r.get_data_ptr()[i] = mMem[i + tmp]; 125 } 126 127 } else { 128 for (unsigned int i = 0; i < num_bytes; ++i) { 129 mMem[i + tmp] = r.get_data_ptr()[i]; 130 } 131 } 132 return num_bytes; 133 } 134 135 bool myGetDMIPtr(transaction_type& trans, 136 tlm::tlm_dmi& dmi_data) 137 { 138 // notify DMI invalidation, just to check if this reaches the 139 // initiators properly 140 m_invalidate_dmi_event.notify(m_invalidate_dmi_time); 141 142 // Check for DMI extension: 143 my_extension * tmp_ext; 144 trans.get_extension(tmp_ext); 145 if (tmp_ext) 146 { 147 std::cout << name() << ": get_direct_mem_ptr OK, extension data = " 148 <<tmp_ext->m_data << std::endl; 149 } 150 else 151 { 152 std::cout << name() << ", get_direct_mem_ptr ERROR: " 153 << "didn't get pointer to extension" 154 << std::endl; 155 } 156 if (trans.get_address() < 400) { 157 dmi_data.allow_read_write(); 158 dmi_data.set_start_address(0x0); 159 dmi_data.set_end_address(399); 160 dmi_data.set_dmi_ptr(mMem); 161 dmi_data.set_read_latency(sc_core::sc_time(100, sc_core::SC_NS)); 162 dmi_data.set_write_latency(sc_core::sc_time(10, sc_core::SC_NS)); 163 return true; 164 165 } else { 166 // should not happen 167 dmi_data.set_start_address(trans.get_address()); 168 dmi_data.set_end_address(trans.get_address()); 169 return false; 170 171 } 172 } 173 174 void invalidate_dmi_method() 175 { 176 sc_dt::uint64 start_address = 0x0; 177 sc_dt::uint64 end_address = 399; 178 socket->invalidate_direct_mem_ptr(start_address, end_address); 179 } 180private: 181 unsigned char mMem[400]; 182 sc_core::sc_event m_invalidate_dmi_event; 183 sc_core::sc_time m_invalidate_dmi_time; 184}; 185 186#endif 187