test07.cpp revision 12855:588919e0e4aa
1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20/***************************************************************************** 21 22 test01.cpp -- Test sc_vector -- empty bindings 23 24 Original Author: Philipp A. Hartmann, OFFIS, 2011-02-14 25 26 *****************************************************************************/ 27 28/***************************************************************************** 29 30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 31 changes you are making here. 32 33 Name, Affiliation, Date: 34 Description of Modification: 35 36 *****************************************************************************/ 37 38#include "systemc.h" 39 40SC_MODULE( sub_module ) 41{ 42 sc_in<bool> in; 43 SC_CTOR(sub_module) {} 44}; 45 46SC_MODULE( module ) 47{ 48 // vector of sub-modules 49 sc_vector< sub_module > m_sub_vec; 50 51 // vector of ports 52 sc_vector< sc_in<bool> > in_vec; 53 54 module( sc_core::sc_module_name, unsigned n_sub ) 55 : m_sub_vec( "sub_modules" ) 56 , in_vec( "in_vec" ) 57 { 58 // bind ports of submodules (before initialisation of module vector) 59 do_bind(); 60 61 // initialise module vector 62 m_sub_vec.init( n_sub ); 63 64 // bind ports of submodules (before initialisation of port vector) 65 do_bind(); 66 67 // delayed initialisation of port vector 68 in_vec.init( n_sub ); 69 70 // bind ports of submodules (should be fine now) 71 do_bind(); 72 } 73 74 void do_bind() 75 { 76 try { 77 // bind ports of sub-modules -- sc_assemble_vector 78 sc_assemble_vector( m_sub_vec, &sub_module::in ).bind( in_vec ); 79 } catch( sc_report const & rpt ) { 80 std::cout << rpt.what() << std::endl; 81 } 82 } 83}; 84 85int sc_main(int , char* []) 86{ 87 module m("dut", 4); 88 sc_vector< sc_signal<bool> > s("sig"); 89 90 // bind ports to signals -- before initialisation of signal vector 91 m.in_vec( s ); 92 93 s.init(4); 94 95 // bind empty range 96 m.in_vec( s.begin(), s.begin() ); 97 98 // bind with full range 99 m.in_vec( s ); 100 101 sc_start( SC_ZERO_TIME ); 102 103 cout << "Success" << endl; 104 return 0; 105} 106