test12.cpp revision 12855:588919e0e4aa
1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20/***************************************************************************** 21 22 test12.cpp -- 23 24 Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 25 26 *****************************************************************************/ 27 28/***************************************************************************** 29 30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 31 changes you are making here. 32 33 Name, Affiliation, Date: 34 Description of Modification: 35 36 *****************************************************************************/ 37 38#include "systemc.h" 39 40SC_MODULE( proc1 ) 41{ 42 SC_HAS_PROCESS( proc1 ); 43 44 sc_in<bool> clk; 45 sc_signal<sc_int<10> >& bv; 46 sc_signal<sc_uint<10> >& sv; 47 48 sc_int<10> obj1; 49 sc_uint<10> obj2; 50 51 proc1( sc_module_name NAME, 52 sc_signal<bool>& CLK, 53 sc_signal<sc_int<10> >& BV, 54 sc_signal<sc_uint<10> >& SV ) 55 : bv(BV), sv(SV) 56 { 57 clk(CLK); 58 SC_THREAD( entry ); 59 sensitive << clk; 60 obj1 = 0; 61 obj2 = 0; 62 bv.write(0); 63 sv.write(0); 64 } 65 66 void entry(); 67}; 68 69void proc1::entry() 70{ 71 wait(); 72 while(true) { 73 obj1 = 3; 74 obj2 = 7; 75 bv = obj1; 76 sv = obj2; 77 wait(); 78 obj1 = -3; 79 obj2 = 5; 80 bv = obj1; 81 sv = obj2; 82 wait(); 83 } 84} 85 86 87int sc_main(int ac, char *av[]) 88{ 89 sc_trace_file *tf; 90 sc_signal<bool> clock; 91 sc_signal<sc_int<10> > bv; 92 sc_signal<sc_uint<10> > sv; 93 94 proc1 P1("P1", clock, bv, sv); 95 96 tf = sc_create_vcd_trace_file("test12"); 97 sc_trace(tf, P1.obj1, "Signed"); 98 sc_trace(tf, P1.obj2, "Unsigned"); 99 sc_trace(tf, bv, "BV"); 100 sc_trace(tf, sv, "SV"); 101 102 clock.write(0); 103 sc_start(0, SC_NS); 104 for (int i = 0; i< 10; i++) { 105cerr << sc_time_stamp() << endl; 106 clock.write(1); 107 sc_start(10, SC_NS); 108cerr << sc_time_stamp() << endl; 109 clock.write(0); 110 sc_start(10, SC_NS); 111cerr << sc_time_stamp() << endl; 112 } 113 114 sc_close_vcd_trace_file( tf ); 115 116 return 0; 117} 118