test09.cpp revision 12855:588919e0e4aa
1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20/***************************************************************************** 21 22 test09.cpp -- 23 24 Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 25 26 *****************************************************************************/ 27 28/***************************************************************************** 29 30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 31 changes you are making here. 32 33 Name, Affiliation, Date: 34 Description of Modification: 35 36 *****************************************************************************/ 37 38#include "systemc.h" 39 40SC_MODULE( proc1 ) 41{ 42 SC_HAS_PROCESS( proc1 ); 43 44 sc_in<bool> clk; 45 sc_signal<int>& Isig; 46 sc_signal<char>& Csig; 47 sc_signal<float>& Fsig; 48 sc_signal<sc_logic>& Lsig; 49 50 proc1( sc_module_name NAME, 51 sc_signal<bool>& CLK, 52 sc_signal<int>& ISIG, 53 sc_signal<char>& CSIG, 54 sc_signal<float>& FSIG, 55 sc_signal<sc_logic>& LSIG ) 56 : Isig(ISIG), Csig(CSIG), Fsig(FSIG), Lsig(LSIG) 57 { 58 clk(CLK); 59 SC_THREAD( entry ); 60 sensitive << clk; 61 Isig = 0; 62 Csig = 0; 63 Fsig = 0.0; 64 Lsig = SC_LOGIC_0;//'0'; 65 } 66 67 void entry(); 68}; 69 70void proc1::entry() 71{ 72 wait(); 73 while(true) { 74 Isig = 1023; 75 Csig = 15; 76 Fsig = -4; 77 Lsig = SC_LOGIC_X;//'x'; 78 wait(); 79 Isig = 10; 80 Csig = 8; 81 Fsig = 1000.23456; 82 Lsig = SC_LOGIC_Z;//'z'; 83 wait(); 84 } 85} 86 87 88int sc_main(int ac, char *av[]) 89{ 90 sc_trace_file *tf; 91 sc_signal<bool> clock; 92 sc_signal<int> I; 93 sc_signal<char> C; 94 sc_signal<float> F; 95 sc_signal<sc_logic> L; 96 97 proc1 P1("P1", clock, I, C, F, L); 98 99 tf = sc_create_vcd_trace_file("test09"); 100 sc_trace(tf, clock, "Clock"); 101 sc_trace(tf, I, "Int"); 102 sc_trace(tf, C, "Char"); 103 sc_trace(tf, F, "Float"); 104 sc_trace(tf, L, "Logic"); 105 106 clock.write(0); 107 sc_start(0, SC_NS); 108 for (int i = 0; i< 10; i++) { 109 clock.write(1); 110 sc_start(10, SC_NS); 111 clock.write(0); 112 sc_start(10, SC_NS); 113 } 114 115 sc_close_vcd_trace_file( tf ); 116 117 return 0; 118} 119