resolved_sig.cpp revision 12855:588919e0e4aa 
1/*****************************************************************************
2
3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4  more contributor license agreements.  See the NOTICE file distributed
5  with this work for additional information regarding copyright ownership.
6  Accellera licenses this file to you under the Apache License, Version 2.0
7  (the "License"); you may not use this file except in compliance with the
8  License.  You may obtain a copy of the License at
9
10    http://www.apache.org/licenses/LICENSE-2.0
11
12  Unless required by applicable law or agreed to in writing, software
13  distributed under the License is distributed on an "AS IS" BASIS,
14  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15  implied.  See the License for the specific language governing
16  permissions and limitations under the License.
17
18 *****************************************************************************/
19
20/*****************************************************************************
21
22  resolved_sig.cpp --
23
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32
33      Name, Affiliation, Date:
34  Description of Modification:
35
36 *****************************************************************************/
37
38#include "systemc.h"
39
40                /**************************************/
41
42SC_MODULE( stimgen )
43{
44    SC_HAS_PROCESS( stimgen );
45
46    // Inputs
47    sc_in_clk  clk;
48    sc_in<int> result;
49
50    // Outputs
51    sc_out<int>  in1;
52    sc_out<int>  in2;
53    sc_out<bool> ready;
54    sc_out_rv<8> bus;
55
56    // Constructor
57    stimgen( sc_module_name        NAME,
58	     sc_clock&             TICK,
59	     sc_signal<int>& RESULT,
60	     sc_signal<int>&       IN1,
61	     sc_signal<int>&       IN2,
62	     sc_signal<bool>&      READY,
63	     sc_signal_rv<8>&      BUS )
64    {
65	SC_CTHREAD( entry, clk.pos() );
66        clk( TICK );
67        result( RESULT );
68        in1( IN1 );
69        in2( IN2 );
70        ready( READY );
71		bus( BUS );
72    }
73
74    void entry();
75};
76
77                /**************************************/
78
79SC_MODULE( datawidth )
80{
81    SC_HAS_PROCESS( datawidth );
82
83    // Inputs
84    sc_in_clk      clk;
85    sc_in<int>     in1;
86    sc_in<int>     in2;
87    sc_in<bool>    ready;
88    sc_inout_rv<8> bus;
89
90    // Outputs
91    sc_out<int> result;
92
93    // Constructor
94    datawidth( sc_module_name         NAME,
95	       sc_clock&              TICK,
96	       sc_signal<int>&  IN1,
97	       sc_signal<int>&  IN2,
98	       sc_signal<bool>& READY,
99	       sc_signal<int>&        RESULT,
100	       sc_signal_rv<8>&       BUS )
101    {
102	SC_CTHREAD( entry, clk.pos() );
103        clk( TICK );
104        in1( IN1 );
105        in2( IN2 );
106        ready( READY );
107        bus( BUS );
108        result( RESULT );
109    }
110
111    void entry();
112};
113
114                /*******************************************/
115
116void
117datawidth::entry()
118{
119    int tmp_a;
120    int	tmp_b;
121    int tmp_result;
122
123    while (true) {
124
125	// HANDSHAKING
126	do { wait(); } while ( ready != 1 );
127
128	// COMPUTATION
129	tmp_a = in1.read();
130	tmp_b = in2.read();
131	tmp_result = tmp_a + tmp_b;
132	cout << ";    reading from bus=" << bus.read() << endl;
133	sc_lv<8> lv( '0' );
134	lv[1] = lv[3] = lv[5] = lv[7] = 1;
135	cout << "datawidth writing to bus: " << lv << endl;
136	bus.write( lv );
137
138	// WRITE OUTPUT
139	result.write( tmp_result ); // result = in1 + in2
140	wait();
141    }
142}
143
144                /*****************************************/
145
146void
147stimgen::entry()
148{
149    int i;
150    int j;
151
152    ready.write( 0 );
153
154    for( i = 0; i < 6; i ++ ) { // integer in1 (6 bits of data)
155	for( j = 0; j < 6; j ++ ) { // integer in2 (6 bits of data)
156	    in1.write( i );
157	    in2.write( j );
158	    ready.write( 1 );
159	    sc_lv<8> lv( sc_logic( i % 4 ) );
160	    lv[1] = lv[3] = lv[5] = lv[7] = j % 4;
161	    cout << "writing to bus: " << lv << flush;
162	    bus.write( lv );
163	    wait();
164
165	    ready.write( 0 );
166	    wait();
167
168	    // cout << in1.read() << " + " << in2.read()
169	    //	    << " = " << result.read() << endl;
170	}
171    }
172
173    sc_stop();
174}
175
176                /***************************************/
177		/*				       */
178		/*	int = int + int		       */
179                /*                                     */
180                /*      Max addition is 63 + 63        */
181		/*				       */
182                /***************************************/
183
184int
185sc_main( int ac, char *av[] )
186{
187    // Signal Instantiation
188    sc_signal<int> in1( "in1" );
189    sc_signal<int> in2( "in2" );
190    sc_signal<int> result( "result" );
191    sc_signal<bool> ready( "ready" );
192    sc_signal_rv<8> bus( "bus" );
193
194    // Clock Instantiation
195    sc_clock clk( "clock", 10, SC_NS, 0.5, 0, SC_NS );
196
197    // Process Instantiation
198    datawidth D1( "D1", clk, in1, in2, ready, result, bus );
199    stimgen T1( "T1", clk, result, in1, in2, ready,bus );
200
201    // Simulation Run Control
202    sc_start();
203
204    return 0;
205}
206