test8.cpp revision 12855:588919e0e4aa 
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20/*****************************************************************************
21
22  test8.cpp --
23
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
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33      Name, Affiliation, Date:
34  Description of Modification:
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36 *****************************************************************************/
37
38// $Log: test8.cpp,v $
39// Revision 1.1.1.1  2006/12/15 20:26:23  acg
40// systemc_tests-2.3
41//
42// Revision 1.2  2006/01/24 21:05:50  acg
43//  Andy Goodrich: replacement of deprecated features with their non-deprecated
44//  counterparts.
45//
46
47/*
48  Corner case testing for new scheduler.
49  Case 5: Checking multiple clock transitions at the same time
50  */
51
52#include "systemc.h"
53
54SC_MODULE( triga )
55{
56  SC_HAS_PROCESS( triga );
57
58  sc_in<bool> clock;
59  sc_signal<int>& out;
60
61  int i;
62
63  triga(sc_module_name NAME,
64	sc_signal_in_if<bool>& CLOCK,
65	sc_signal<int>& OUT_)
66    : out(OUT_)
67  {
68    clock(CLOCK);
69    SC_METHOD( entry );
70    sensitive << clock;
71    i = 0;
72    out = i++;
73  }
74
75  void entry()
76  {
77    out = i++;
78  }
79};
80
81SC_MODULE( watcher )
82{
83  SC_HAS_PROCESS( watcher );
84
85  sc_in<bool> clock1;
86  sc_in<bool> clock2;
87  const sc_signal<int>& in1;
88  const sc_signal<int>& in2;
89  const sc_signal<int>& in3;
90  const sc_signal<int>& in4;
91
92  watcher(sc_module_name NAME,
93	  sc_signal_in_if<bool>& CLOCK1,
94	  sc_signal_in_if<bool>& CLOCK2,
95	  const sc_signal<int>& IN1,
96	  const sc_signal<int>& IN2,
97	  const sc_signal<int>& IN3,
98	  const sc_signal<int>& IN4)
99    : in1(IN1), in2(IN2), in3(IN3), in4(IN4)
100  {
101    clock1(CLOCK1);
102    clock2(CLOCK2);
103    SC_METHOD( entry );
104    sensitive << clock1; sensitive << clock2;
105    sensitive << in1; sensitive << in2; sensitive << in3; sensitive << in4;
106  }
107
108  void entry()
109  {
110    cout << "[ ";
111    if (clock1.posedge()) cout << "Posedge(1) - ";
112    if (clock1.negedge()) cout << "Negedge(1) - ";
113    if (clock2.posedge()) cout << "Posedge(2) - ";
114    if (clock2.negedge()) cout << "Negedge(2) - ";
115    if (in1.event()) cout << "Sync1 Out = " << in1.read() << " - ";
116    if (in2.event()) cout << "ASync1 Out = " << in2.read() << " - ";
117    if (in3.event()) cout << "Sync2 Out = " << in3.read() << " - ";
118    if (in4.event()) cout << "ASync2 Out = " << in4.read() << " - ";
119    cout << "]" << endl;
120  }
121};
122
123
124SC_MODULE( trigp )
125{
126  SC_HAS_PROCESS( trigp );
127
128  sc_in<bool> clk;
129
130  sc_signal<int>& out;
131
132  trigp(sc_module_name NAME,
133	sc_signal_in_if<bool>& CLK,
134	sc_signal<int>& OUT_)
135    : out(OUT_)
136  {
137    clk(CLK);
138    SC_CTHREAD( entry, clk.pos() );
139    out = 0;
140  }
141
142  void entry()
143  {
144    int i = 11;
145    while (true) {
146      out = i++;
147      wait();
148    }
149  }
150};
151
152int
153sc_main(int ac, char *av[])
154{
155  // sc_clock clock1("Clock1", 20, SC_NS, 0.5);
156  // sc_clock clock2("Clock2", 20, SC_NS, 0.5);
157  sc_signal<bool> clock1( "Clock1" );
158  sc_signal<bool> clock2( "Clock2" );
159
160  sc_signal<int> sig1, sig2, sig3, sig4;
161
162  triga T1("T1", clock1, sig2);
163  triga T2("T2", clock2, sig4);
164  trigp T3("T3", clock1, sig1);
165  trigp T4("T4", clock2, sig3);
166  watcher W("W", clock1, clock2, sig1, sig2, sig3, sig4);
167
168  sc_trace_file *tf = sc_create_vcd_trace_file("systemc");
169  sc_trace(tf, clock1, "Clock1");
170  sc_trace(tf, clock2, "Clock2");
171  sc_trace(tf, sig1, "Sync1");
172  sc_trace(tf, sig2, "Async1");
173  sc_trace(tf, sig3, "Sync2");
174  sc_trace(tf, sig4, "Async2");
175
176  sc_start(0, SC_NS);
177  clock1 = 0;
178  clock2 = 0;
179  sc_start(5, SC_NS);
180  for (int i = 0; i< 10; i++) {
181    clock1 = 1; clock2 = 1;
182    sc_start(5, SC_NS);
183    clock1 = 0; clock2 = 0;
184    sc_start(5, SC_NS);
185  }
186  return 0;
187}
188