test7.cpp revision 12855:588919e0e4aa
1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20/***************************************************************************** 21 22 test7.cpp -- 23 24 Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 25 26 *****************************************************************************/ 27 28/***************************************************************************** 29 30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 31 changes you are making here. 32 33 Name, Affiliation, Date: 34 Description of Modification: 35 36 *****************************************************************************/ 37 38/* 39 Corner case testing for new scheduler. 40 Case 5: Checking multiple clock transitions at the same time 41 */ 42 43#include "systemc.h" 44 45SC_MODULE( triga ) 46{ 47 SC_HAS_PROCESS( triga ); 48 49 sc_in<bool> clock; 50 sc_signal<int>& out; 51 52 int i; 53 54 triga(sc_module_name NAME, 55 sc_signal_in_if<bool>& CLOCK, 56 sc_signal<int>& OUT_) 57 : out(OUT_) 58 { 59 clock(CLOCK); 60 SC_METHOD( entry ); 61 sensitive << clock; 62 i = 0; 63 out = i++; 64 } 65 66 void entry() 67 { 68 out = i++; 69 } 70}; 71 72SC_MODULE( watcher ) 73{ 74 SC_HAS_PROCESS( watcher ); 75 76 sc_in<bool> clock1; 77 sc_in<bool> clock2; 78 const sc_signal<int>& in1; 79 const sc_signal<int>& in2; 80 const sc_signal<int>& in3; 81 const sc_signal<int>& in4; 82 83 watcher(sc_module_name NAME, 84 sc_signal_in_if<bool>& CLOCK1, 85 sc_signal_in_if<bool>& CLOCK2, 86 const sc_signal<int>& IN1, 87 const sc_signal<int>& IN2, 88 const sc_signal<int>& IN3, 89 const sc_signal<int>& IN4) 90 : in1(IN1), in2(IN2), in3(IN3), in4(IN4) 91 { 92 clock1(CLOCK1); 93 clock2(CLOCK2); 94 SC_METHOD( entry ); 95 sensitive << clock1 << clock2; 96 sensitive << in1 << in2 << in3 << in4; 97 } 98 99 void entry() 100 { 101 cout << "[ "; 102 if (clock1.posedge()) cout << "Posedge(1) - "; 103 if (clock1.negedge()) cout << "Negedge(1) - "; 104 if (clock2.posedge()) cout << "Posedge(2) - "; 105 if (clock2.negedge()) cout << "Negedge(2) - "; 106 if (in1.event()) cout << "Sync1 Out = " << in1.read() << " - "; 107 if (in2.event()) cout << "ASync1 Out = " << in2.read() << " - "; 108 if (in3.event()) cout << "Sync2 Out = " << in3.read() << " - "; 109 if (in4.event()) cout << "ASync2 Out = " << in4.read() << " - "; 110 cout << "]" << endl; 111 } 112}; 113 114 115SC_MODULE( trigp ) 116{ 117 SC_HAS_PROCESS( trigp ); 118 119 sc_in<bool> clk; 120 121 sc_signal<int>& out; 122 123 trigp(sc_module_name NAME, 124 sc_signal_in_if<bool>& CLK, 125 sc_signal<int>& OUT_) 126 : out(OUT_) 127 { 128 clk(CLK); 129 SC_CTHREAD( entry, clk.pos() ); 130 out = 0; 131 } 132 133 void entry() 134 { 135 int i = 11; 136 while (true) { 137 out = i++; 138 wait(); 139 } 140 } 141}; 142 143int 144sc_main(int ac, char *av[]) 145{ 146 sc_clock clock1("Clock1", 20, SC_NS, 0.5); 147 sc_clock clock2("Clock2", 40, SC_NS, 0.5); 148 149 sc_signal<int> sig1, sig2, sig3, sig4; 150 151 triga T1("T1", clock1, sig2); 152 triga T2("T2", clock2, sig4); 153 trigp T3("T3", clock1, sig1); 154 trigp T4("T4", clock2, sig3); 155 watcher W("W", clock1, clock2, sig1, sig2, sig3, sig4); 156 157 sc_trace_file *tf = sc_create_vcd_trace_file("systemc"); 158 sc_trace(tf, clock1, "Clock1"); 159 sc_trace(tf, clock2, "Clock2"); 160 sc_trace(tf, sig1, "Sync1"); 161 sc_trace(tf, sig2, "Async1"); 162 sc_trace(tf, sig3, "Sync2"); 163 sc_trace(tf, sig4, "Async2"); 164 165 sc_start(100, SC_NS); 166 return 0; 167} 168