test6.cpp revision 12855:588919e0e4aa 
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20/*****************************************************************************
21
22  test6.cpp --
23
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32
33      Name, Affiliation, Date:
34  Description of Modification:
35
36 *****************************************************************************/
37
38/*
39  Corner case testing for new scheduler.
40  Case 5: Checking multiple clock transitions at the same time
41  */
42
43#include "systemc.h"
44
45SC_MODULE( triga )
46{
47  SC_HAS_PROCESS( triga );
48
49  sc_in<bool> clock;
50  sc_signal<int>& out;
51
52  int i;
53
54  triga(sc_module_name NAME,
55	sc_signal_in_if<bool>& CLOCK,
56	sc_signal<int>& OUT_)
57    : out(OUT_)
58  {
59    clock(CLOCK);
60    SC_METHOD( entry );
61    sensitive << clock;
62    i = 0;
63    out = i++;
64  }
65
66  void entry()
67  {
68    out = i++;
69  }
70};
71
72SC_MODULE( watcher )
73{
74  SC_HAS_PROCESS( watcher );
75
76  sc_in<bool> clock1;
77  sc_in<bool> clock2;
78  const sc_signal<int>& in1;
79  const sc_signal<int>& in2;
80  const sc_signal<int>& in3;
81  const sc_signal<int>& in4;
82
83  watcher(sc_module_name NAME,
84	  sc_signal_in_if<bool>& CLOCK1,
85	  sc_signal_in_if<bool>& CLOCK2,
86	  const sc_signal<int>& IN1,
87	  const sc_signal<int>& IN2,
88	  const sc_signal<int>& IN3,
89	  const sc_signal<int>& IN4)
90    : in1(IN1), in2(IN2), in3(IN3), in4(IN4)
91  {
92    clock1(CLOCK1); clock2(CLOCK2);
93    SC_METHOD( entry );
94    sensitive << clock1 << clock2 << in1 << in2 << in3 << in4;
95  }
96
97  void entry()
98  {
99    cout << "[ ";
100    if (clock1.posedge()) cout << "Posedge(1) - ";
101    if (clock1.negedge()) cout << "Negedge(1) - ";
102    if (clock2.posedge()) cout << "Posedge(2) - ";
103    if (clock2.negedge()) cout << "Negedge(2) - ";
104    if (in1.event()) cout << "Sync1 Out = " << in1.read() << " - ";
105    if (in2.event()) cout << "ASync1 Out = " << in2.read() << " - ";
106    if (in3.event()) cout << "Sync2 Out = " << in3.read() << " - ";
107    if (in4.event()) cout << "ASync2 Out = " << in4.read() << " - ";
108    cout << "]" << endl;
109  }
110};
111
112
113SC_MODULE( trigp )
114{
115  SC_HAS_PROCESS( trigp );
116
117  sc_in<bool> clk;
118
119  sc_signal<int>& out;
120
121  trigp(sc_module_name NAME,
122	sc_signal_in_if<bool>& CLK,
123	sc_signal<int>& OUT_)
124    : out(OUT_)
125  {
126    clk(CLK);
127    SC_CTHREAD( entry, clk.pos() );
128    out = 0;
129  }
130
131  void entry()
132  {
133    int i = 11;
134    while (true) {
135      out = i++;
136      wait();
137    }
138  }
139};
140
141int
142sc_main(int ac, char *av[])
143{
144  sc_clock clock1("Clock1", 20, SC_NS, 0.5);
145  sc_clock clock2("Clock2", 20, SC_NS, 0.5);
146
147  sc_signal<int> sig1, sig2, sig3, sig4;
148
149  triga T1("T1", clock1, sig2);
150  triga T2("T2", clock2, sig4);
151  trigp T3("T3", clock1, sig1);
152  trigp T4("T4", clock2, sig3);
153  watcher W("W", clock1, clock2, sig1, sig2, sig3, sig4);
154
155  sc_trace_file *tf = sc_create_vcd_trace_file("systemc");
156  sc_trace(tf, clock1, "Clock1");
157  sc_trace(tf, clock2, "Clock2");
158  sc_trace(tf, sig1, "Sync1");
159  sc_trace(tf, sig2, "Async1");
160  sc_trace(tf, sig3, "Sync2");
161  sc_trace(tf, sig4, "Async2");
162
163  sc_start(100, SC_NS);
164  return 0;
165}
166