test4.cpp revision 12855:588919e0e4aa 
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20/*****************************************************************************
21
22  test4.cpp --
23
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32
33      Name, Affiliation, Date:
34  Description of Modification:
35
36 *****************************************************************************/
37
38/*
39  Corner case testing for new scheduler.
40  Case 4: Checking gated clocks and triggering of processes
41  */
42
43#include "systemc.h"
44
45SC_MODULE( cgater )
46{
47  SC_HAS_PROCESS( cgater );
48
49  const sc_signal<bool>& gate;
50  sc_in<bool>  clock_in;
51  sc_out<bool> clock_out;
52
53  cgater(sc_module_name NAME,
54	 const sc_signal<bool>& GATE,
55	 sc_signal_in_if<bool>& CLOCK_IN,
56	 sc_signal_out_if<bool>& CLOCK_OUT)
57    : gate(GATE)
58  {
59    clock_in(CLOCK_IN);
60    clock_out(CLOCK_OUT);
61    SC_METHOD( entry );
62    sensitive << gate;
63    sensitive << clock_in;
64  }
65
66  void entry()
67  {
68    clock_out = clock_in & gate;
69  }
70};
71
72SC_MODULE( watcher )
73{
74  SC_HAS_PROCESS( watcher );
75
76  const sc_signal<bool>& gate;
77  sc_in<bool> clock;
78  sc_in<bool> dclock;
79  const sc_signal<int>& a;
80
81  watcher(sc_module_name NAME,
82	  const sc_signal<bool>& GATE,
83	  sc_signal_in_if<bool>& CLOCK,
84	  sc_signal_in_if<bool>& DCLOCK,
85	  const sc_signal<int>& A)
86    : gate(GATE), a(A)
87  {
88    clock(CLOCK);
89    dclock(DCLOCK);
90    SC_METHOD( entry );
91    sensitive << clock;
92    sensitive << a;
93    sensitive << gate;
94    sensitive << dclock;
95  }
96
97  void entry()
98  {
99    cout << "[ ";
100    if (clock.posedge()) cout << "Posedge - ";
101    if (clock.negedge()) cout << "Negedge - ";
102    if (dclock.posedge()) cout << "Posedge(D) - ";
103    if (dclock.negedge()) cout << "Negedge(D) - ";
104    if (a.event()) cout << "A = " << a.read() << " - ";
105    if (gate.event()) cout << "Gate = " << gate.read() << " - ";
106    cout << "]" << endl;
107  }
108};
109
110
111SC_MODULE( gategen )
112{
113  SC_HAS_PROCESS( gategen );
114
115  sc_in<bool> clk;
116
117  sc_signal<bool>& gate;
118
119  gategen(sc_module_name NAME,
120	  sc_signal_in_if<bool>& CLK,
121	  sc_signal<bool>& GATE)
122    : gate(GATE)
123  {
124    clk(CLK);
125    SC_CTHREAD( entry, clk.pos() );
126    gate = 1;
127  }
128
129  void entry()
130  {
131    while (true) {
132      gate = 1; wait(3);
133      gate = 0; wait (3);
134    }
135  }
136};
137
138SC_MODULE( trigp )
139{
140  SC_HAS_PROCESS( trigp );
141
142  sc_in<bool> clk;
143
144  sc_signal<int>& out;
145
146  trigp(sc_module_name NAME,
147	sc_signal_in_if<bool>& CLK,
148	sc_signal<int>& OUT_)
149    : out(OUT_)
150  {
151    clk(CLK);
152    SC_CTHREAD( entry, clk.pos() );
153    out = 0;
154  }
155
156  void entry()
157  {
158    int i = 11;
159    while (true) {
160      out = i++;
161      wait();
162    }
163  }
164};
165
166int
167sc_main(int ac, char *av[])
168{
169  // sc_clock clock1("Clock1", 20, SC_NS, 0.5);
170  // sc_clock dclock("Derived");
171  sc_signal<bool> clock1( "Clock1" );
172  sc_signal<bool> dclock( "Derived" );
173
174  sc_signal<bool> Gate;
175  sc_signal<int> Output;
176
177  cgater CG("CG", Gate, clock1, dclock);
178  watcher W("W", Gate, clock1, dclock, Output);
179  gategen G("G", clock1, Gate);
180  trigp T("T", dclock, Output);
181
182  sc_trace_file *tf = sc_create_vcd_trace_file("systemc");
183  sc_trace(tf, clock1, "Clock");
184  sc_trace(tf, dclock, "Dclock");
185  sc_trace(tf, Gate, "Gate");
186  sc_trace(tf, Output, "Out");
187
188  sc_start(0, SC_NS);
189  clock1.write(0);
190  sc_start(5, SC_NS);
191  for (int i=0; i < 30; i++) {
192    clock1.write(1);
193    sc_start(5, SC_NS);
194    clock1.write(0);
195    sc_start(5, SC_NS);
196  }
197
198  return 0;
199}
200