test2.cpp revision 12855:588919e0e4aa
1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20/***************************************************************************** 21 22 test2.cpp -- 23 24 Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 25 26 *****************************************************************************/ 27 28/***************************************************************************** 29 30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 31 changes you are making here. 32 33 Name, Affiliation, Date: 34 Description of Modification: 35 36 *****************************************************************************/ 37 38/* 39 Corner case testing for new scheduler. 40 Case 2: Checking single cycle interaction between 41 sc_sync and async, in conjunction with triggering of 42 sc_sync and async that are sensitive to a clock 43 */ 44 45#include "systemc.h" 46 47SC_MODULE( syncproc ) 48{ 49 SC_HAS_PROCESS( syncproc ); 50 51 sc_in<bool> clk; 52 53 const sc_signal<int>& in1; 54 const sc_signal<int>& in2; 55 sc_signal<int>& out; 56 57 syncproc(sc_module_name NAME, 58 sc_signal_in_if<bool>& CLK, 59 const sc_signal<int>& IN1, 60 const sc_signal<int>& IN2, 61 sc_signal<int>& OUT_) 62 : in1(IN1), in2(IN2), out(OUT_) 63 { 64 clk(CLK); 65 SC_CTHREAD( entry, clk.pos() ); 66 out = 0; 67 } 68 69 void entry() 70 { 71 int i = 100; 72 while (true) { 73 out = i; 74 wait(); 75 while (in2.read() != i) { 76 cout << "Sync: Value written = " << i << " value1 read = " << in1.read() << " value2 read = " << in2.read() << endl; 77 wait(); 78 cout << "Waited one cycle\n" << endl; 79 } 80 i++; 81 } 82 } 83}; 84 85SC_MODULE( asyncproc ) 86{ 87 SC_HAS_PROCESS( asyncproc ); 88 89 const sc_signal<int>& in; 90 sc_signal<int>& out; 91 sc_in<bool> clock; 92 93 asyncproc(sc_module_name NAME, 94 const sc_signal<int>& IN_, 95 sc_signal<int>& OUT_, 96 sc_signal_in_if<bool>& CLOCK) 97 : in(IN_), out(OUT_) 98 { 99 clock(CLOCK); 100 out = 0; 101 SC_THREAD( entry ); 102 sensitive << in; 103 } 104 105 void entry() 106 { 107 wait(); 108 while (true) { 109 out = in + 10; 110 cout << "AsyncProc: Value read = " << in.read() << endl; 111 wait(); 112 } 113 } 114}; 115 116SC_MODULE( asyncblock ) 117{ 118 SC_HAS_PROCESS( asyncblock ); 119 120 const sc_signal<int>& in; 121 sc_signal<int>& out; 122 sc_in<bool> clock; 123 124 asyncblock(sc_module_name NAME, 125 const sc_signal<int>& IN_, 126 sc_signal<int>& OUT_, 127 sc_signal_in_if<bool>& CLOCK) 128 : in(IN_), out(OUT_) 129 { 130 clock(CLOCK); 131 out = 0; 132 SC_METHOD( entry ); 133 sensitive << clock; 134 } 135 136 void entry() 137 { 138 if (clock.posedge()) { 139 out = in; 140 cout << "AsyncBlock: Value read = " << in.read() << endl; 141 } 142 else { 143 cout << "Seen other edge" << endl; 144 } 145 } 146}; 147 148 149int 150sc_main(int ac, char *av[]) 151{ 152 sc_signal<int> a, b, c; 153 154 sc_clock clock("Clock", 20, SC_NS, 0.5); 155 156 syncproc P1("P1", clock, a, b, c); 157 asyncproc P2("P2", c, a, clock); 158 asyncblock P3("P3", c, b, clock); 159 160 sc_trace_file *tf = sc_create_vcd_trace_file("systemc"); 161 tf->set_time_unit(1, SC_NS); 162 sc_trace(tf, a, "SYNC-IN1"); 163 sc_trace(tf, b, "SYNC-IN2"); 164 sc_trace(tf, c, "SYNC2-OUT"); 165 sc_trace(tf, clock, "Clock"); 166 167 sc_start(160, SC_NS); 168 return 0; 169 170} 171