testbench.h revision 12855:588919e0e4aa
1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20/***************************************************************************** 21 22 testbench.h -- 23 24 Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 25 26 *****************************************************************************/ 27 28/***************************************************************************** 29 30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 31 changes you are making here. 32 33 Name, Affiliation, Date: 34 Description of Modification: 35 36 *****************************************************************************/ 37 38/* Filename testbench.h */ 39/* This is the interface file for synchronous process `testbench' */ 40 41#include "systemc.h" 42 43SC_MODULE( testbench ) 44{ 45 SC_HAS_PROCESS( testbench ); 46 47 sc_in_clk clk; 48 49 const sc_signal<int>& Ssum; //input 50 const sc_signal<int>& Sdiff; //input 51 const sc_signal<bool>& adder_sub_done; //input 52 sc_signal<int>& Sa; //output 53 sc_signal<int>& Sb; //output 54 sc_signal<int>& Sc; //output 55 sc_signal<bool>& adder_sub_ready; //output 56 57 //Constructor 58 testbench(sc_module_name NAME, 59 sc_clock& CLK, 60 const sc_signal<int>& SSUM, 61 const sc_signal<int>& SDIFF, 62 const sc_signal<bool>& ADDER_SUB_DONE, 63 sc_signal<int>& SA, 64 sc_signal<int>& SB, 65 sc_signal<int>& SC, 66 sc_signal<bool>& ADDER_SUB_READY) 67 : Ssum(SSUM), Sdiff(SDIFF), 68 adder_sub_done(ADDER_SUB_DONE), 69 Sa(SA), Sb(SB), Sc(SC), adder_sub_ready(ADDER_SUB_READY) 70 71 { 72 clk(CLK); 73 SC_CTHREAD( entry, clk.pos() ); 74 } 75 76 // Process functionality in member function below 77 void entry(); 78}; 79 80 81