stage1_2.h revision 12855:588919e0e4aa
1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20/***************************************************************************** 21 22 stage1_2.h -- 23 24 Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 25 26 *****************************************************************************/ 27 28/***************************************************************************** 29 30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 31 changes you are making here. 32 33 Name, Affiliation, Date: 34 Description of Modification: 35 36 *****************************************************************************/ 37 38/* Filename stage1_2.h */ 39/* This is the interface file for module `stage1_2' */ 40 41#include "systemc.h" 42 43struct stage1_2 : public sc_module { 44 sc_signal<double> sum; // internal signal 45 sc_signal<double> diff; // internal signal 46 47 stage1 S1; // component 48 stage2 S2; // component 49 50 //Constructor 51 stage1_2(sc_module_name NAME, 52 sc_clock& TICK, 53 const sc_signal<double>& IN1, 54 const sc_signal<double>& IN2, 55 sc_signal<double>& PROD, 56 sc_signal<double>& QUOT) 57 : sc_module(NAME), 58 S1("Stage1", TICK, IN1, IN2, sum, diff), 59 S2("Stage2", TICK, sum, diff, PROD, QUOT), 60 sum("SigSum") 61 { 62 } 63}; 64 65 66