ram.h revision 12855:588919e0e4aa
1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20/***************************************************************************** 21 22 ram.h -- 23 24 Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 25 26 *****************************************************************************/ 27 28/***************************************************************************** 29 30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 31 changes you are making here. 32 33 Name, Affiliation, Date: 34 Description of Modification: 35 36 *****************************************************************************/ 37 38/* Filename ram.h */ 39/* This is the interface file for synchronous process 'ram' */ 40 41#include "common.h" 42 43SC_MODULE( ram ) 44{ 45 SC_HAS_PROCESS( ram ); 46 47 sc_in_clk clk; 48 49 const signal_bool_vector32& datain; //input 50 const sc_signal<bool>& cs; //input 51 const sc_signal<bool>& we; //input 52 const signal_bool_vector10& addr; //input 53 signal_bool_vector32& dataout; //output 54 55 // Internal variable 56 int memory[4000]; 57 58 // Parameter 59 const int wait_cycles; // Number of cycles it takes to access memory 60 61 //Constructor 62 ram(sc_module_name NAME, 63 sc_clock& TICK, 64 const signal_bool_vector32& DATAIN, 65 const sc_signal<bool>& CS, 66 const sc_signal<bool>& WE, 67 const signal_bool_vector10& ADDR, 68 signal_bool_vector32& DATAOUT, 69 const int WAIT_CYCLES = 1) 70 : datain(DATAIN), cs(CS), we(WE), 71 addr(ADDR), dataout(DATAOUT), wait_cycles(WAIT_CYCLES) 72 { 73 clk(TICK); 74 SC_CTHREAD( entry, clk.pos() ); 75 } 76 77 // Process functionality in member function below 78 void entry(); 79}; 80 81 82