mean.h revision 12855:588919e0e4aa
1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20/***************************************************************************** 21 22 mean.h -- 23 24 Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 25 26 *****************************************************************************/ 27 28/***************************************************************************** 29 30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 31 changes you are making here. 32 33 Name, Affiliation, Date: 34 Description of Modification: 35 36 *****************************************************************************/ 37 38/* This is the interface file for synchronous process `mean' */ 39 40#include "systemc.h" 41 42typedef sc_signal<sc_bv<24> > signal_bool_vector; 43 44SC_MODULE( mean ) 45{ 46 SC_HAS_PROCESS( mean ); 47 48 sc_in_clk clk; 49 50 const signal_bool_vector& in; //input 51 signal_bool_vector& out; //output 52 const sc_signal<bool>& data_available; //input 53 sc_signal<bool>& send_input; //output 54 sc_signal<bool>& data_ready; //output 55 const sc_signal<bool>& receiver_ready; //input 56 57 //Constructor 58 mean(sc_module_name NAME, 59 sc_clock& CLK, 60 const signal_bool_vector& IN_, 61 signal_bool_vector& OUT_, 62 const sc_signal<bool>& DATA_AVAILABLE, 63 sc_signal<bool>& SEND_INPUT, 64 sc_signal<bool>& DATA_READY, 65 const sc_signal<bool>& RECEIVER_READY) 66 : in(IN_), out(OUT_), receiver_ready(RECEIVER_READY), send_input(SEND_INPUT), data_available(DATA_AVAILABLE), data_ready(DATA_READY) 67 { 68 clk(CLK); 69 SC_CTHREAD( entry, clk.pos() ); 70 } 71 72 // Process functionality in member function below 73 void entry(); 74}; 75