test1.cpp revision 12855:588919e0e4aa 
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3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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6  Accellera licenses this file to you under the Apache License, Version 2.0
7  (the "License"); you may not use this file except in compliance with the
8  License.  You may obtain a copy of the License at
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10    http://www.apache.org/licenses/LICENSE-2.0
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12  Unless required by applicable law or agreed to in writing, software
13  distributed under the License is distributed on an "AS IS" BASIS,
14  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15  implied.  See the License for the specific language governing
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18 *****************************************************************************/
19
20/*****************************************************************************
21
22  test1.cpp --
23
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32
33      Name, Affiliation, Date:
34  Description of Modification:
35
36 *****************************************************************************/
37
38#include <systemc.h>
39#include "types2.h"
40
41void types2::entry(){
42
43  int     tmp1_uns_lv;
44  sc_lv<8>  tmp2_uns_lv;
45  sc_uint<8>        tmp1_uns;
46  sc_uint<8>       tmp2_uns;
47  sc_int<9>       temp_output1;
48  sc_int<8>       temp_output2;
49  sc_lv<9>       output1;
50  int       output2;
51
52  b_new_struct test;
53  a_new_struct test1;
54  // reset_loop
55  out_valid.write(0);
56
57  wait();
58  while (true) {
59    test1 = port_in.read();
60    while(test1.in_valid == (sc_logic)'0') {
61      wait();
62      test1 = port_in.read();
63     }
64    wait();
65
66    //cout << "Starting execution" << endl;
67
68    //reading the inputs
69    tmp1_uns_lv = test1.in_value1;
70    //cout << "read inputs" << endl;
71    tmp2_uns_lv = test1.in_value2;
72    //cout << "read inputs" << endl;
73    tmp1_uns = tmp1_uns_lv;
74    tmp2_uns = tmp2_uns_lv;
75
76    //execute simple operations
77    tmp1_uns++;
78    tmp2_uns--;
79    tmp1_uns_lv = tmp1_uns;
80
81
82    output1 = temp_output1 = tmp1_uns + tmp2_uns;
83    output2 = temp_output2 = tmp1_uns - tmp2_uns;
84
85    wait();
86
87    // write outputs
88
89    test.out_value1 = "000000000";
90    test.out_value2 = tmp1_uns_lv;
91    port_out.write(test);
92
93    out_valid.write(1);
94    wait();
95
96    out_valid.write(0);
97    wait();
98    test.out_value1 = output1;
99    test.out_value2 = output2;
100
101    port_out.write(test);
102    out_valid.write(1);
103    wait();
104
105
106    out_valid.write(0);
107    wait();
108
109}
110}
111// EOF
112
113