main.cpp revision 12855:588919e0e4aa 
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3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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6  Accellera licenses this file to you under the Apache License, Version 2.0
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10    http://www.apache.org/licenses/LICENSE-2.0
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12  Unless required by applicable law or agreed to in writing, software
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20/*****************************************************************************
21
22  main.cpp --
23
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
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33      Name, Affiliation, Date:
34  Description of Modification:
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36 *****************************************************************************/
37
38                /******************************************/
39                /* Main Filename:       main.cc           */
40                /******************************************/
41                /*                                        */
42                /* 7-bit bool = 6-bit bool + 6-bit bool   */
43                /*                                        */
44		/*	Max addition is 63 + 63	          */
45                /*                                        */
46		/* This example explicitly promotes all   */
47		/* variables in the addition to the size  */
48		/* of the largest variable (7-bits).      */
49                /*                                        */
50		/* This matches Verilog semantics.	  */
51                /*                                        */
52                /******************************************/
53
54
55#include "datawidth.h"
56#include "stimgen.h"
57
58int sc_main(int ac, char *av[])
59{
60
61// Signal Instantiation
62  sc_signal_bool_vector6   	  in1 		("in1");
63  sc_signal_bool_vector6   	  in2		("in2");
64  sc_signal_bool_vector7   	  result 	("result");
65  sc_signal<bool> 	  ready 	("ready");
66
67// Clock Instantiation
68  sc_clock clk( "clock", 10, SC_NS, 0.5, 0, SC_NS);
69
70// Process Instantiation
71  datawidth	D1 ("D1", clk, in1, in2, ready, result);
72
73  stimgen	T1 ("T1", clk, result, in1, in2, ready);
74
75// Simulation Run Control
76  sc_start();
77  return 0;
78}
79