main.cpp revision 12855:588919e0e4aa 
1/*****************************************************************************
2
3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4  more contributor license agreements.  See the NOTICE file distributed
5  with this work for additional information regarding copyright ownership.
6  Accellera licenses this file to you under the Apache License, Version 2.0
7  (the "License"); you may not use this file except in compliance with the
8  License.  You may obtain a copy of the License at
9
10    http://www.apache.org/licenses/LICENSE-2.0
11
12  Unless required by applicable law or agreed to in writing, software
13  distributed under the License is distributed on an "AS IS" BASIS,
14  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15  implied.  See the License for the specific language governing
16  permissions and limitations under the License.
17
18 *****************************************************************************/
19
20/*****************************************************************************
21
22  main.cpp --
23
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32
33      Name, Affiliation, Date:
34  Description of Modification:
35
36 *****************************************************************************/
37
38                /***************************************/
39                /* Main Filename:       main.cc        */
40                /***************************************/
41
42#include "concat_port.h"
43#include "stimgen.h"
44
45int sc_main(int ac, char *av[])
46{
47
48// Signal Instantiation
49  signal_bool_vector8  	  a		("a");
50  signal_bool_vector8  	  b		("b");
51  signal_bool_vector8  	  c		("c");
52  signal_bool_vector16 	  d		("d");
53  sc_signal<int>	  mode		("mode");
54  sc_signal<bool>	  ready		("ready");
55  sc_signal<bool>	  done		("done");
56
57// Clock Instantiation
58  sc_clock clk( "clock", 10, SC_NS, 0.5, 0, SC_NS);
59
60// Process Instantiation
61  concat_port	D1 ("D1", clk, a, b, mode, ready, c, d, done);
62
63  stimgen	T1 ("T1", clk, c, d, done, a, b, mode, ready);
64
65// Simulation Run Control
66  sc_start();
67  return 0;
68}
69