rdy.h revision 12855:588919e0e4aa 
1/*****************************************************************************
2
3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4  more contributor license agreements.  See the NOTICE file distributed
5  with this work for additional information regarding copyright ownership.
6  Accellera licenses this file to you under the Apache License, Version 2.0
7  (the "License"); you may not use this file except in compliance with the
8  License.  You may obtain a copy of the License at
9
10    http://www.apache.org/licenses/LICENSE-2.0
11
12  Unless required by applicable law or agreed to in writing, software
13  distributed under the License is distributed on an "AS IS" BASIS,
14  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15  implied.  See the License for the specific language governing
16  permissions and limitations under the License.
17
18 *****************************************************************************/
19
20/*****************************************************************************
21
22  rdy.h --
23
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32
33      Name, Affiliation, Date:
34  Description of Modification:
35
36 *****************************************************************************/
37
38#include "systemc.h"
39
40/******************************************************************************/
41/***************************    rdy Function             **********************/
42/******************************************************************************/
43
44SC_MODULE( RDY )
45{
46  SC_HAS_PROCESS( RDY );
47
48  sc_in_clk clk;
49
50  /*** Input and Output Ports ***/
51  sc_signal<bool>& data;
52
53  /*** Constructor ***/
54  RDY (   sc_module_name        	NAME,
55                sc_clock&		TICK_N,
56                sc_signal<bool>&  	DATA )
57
58    :
59		data (DATA)
60
61    {
62      clk (TICK_N);
63	  SC_CTHREAD( entry, clk.neg() );
64    }
65
66  /*** Call to Process Functionality ***/
67  void entry();
68
69};
70
71void
72RDY::entry()
73{
74  // IMPLICIT wait(); AT FIRST NEGEDGE
75  cout << sc_time_stamp() << " : "	// Time 10
76       << "ready = " << data
77       << "\t\t (RDY) "
78       << endl;
79  data.write(0);
80
81  wait();						// Time 30
82  cout << sc_time_stamp() << " : "
83       << "ready = " << data
84       << "\t\t (RDY) "
85       << endl;
86  data.write(1);
87
88  wait(); 						// Time 50
89  cout << sc_time_stamp() << " : "
90       << "ready = " << data
91       << "\t\t (RDY) "
92       << endl;
93  data.write(0);
94
95  wait(); 						// Time 70
96  cout << sc_time_stamp() << " : "
97       << "ready = " << data
98       << "\t\t (RDY) "
99       << endl;
100  data.write(1);
101
102  wait(); 						// Time 90
103  cout << sc_time_stamp() << " : "
104       << "ready = " << data
105       << "\t\t (RDY) "
106       << endl;
107
108  halt();
109}
110