tb.h revision 12855:588919e0e4aa 
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3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4  more contributor license agreements.  See the NOTICE file distributed
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6  Accellera licenses this file to you under the Apache License, Version 2.0
7  (the "License"); you may not use this file except in compliance with the
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10    http://www.apache.org/licenses/LICENSE-2.0
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12  Unless required by applicable law or agreed to in writing, software
13  distributed under the License is distributed on an "AS IS" BASIS,
14  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15  implied.  See the License for the specific language governing
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19
20/*****************************************************************************
21
22  tb.h --
23
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32
33      Name, Affiliation, Date:
34  Description of Modification:
35
36 *****************************************************************************/
37
38/* Common interface file for test bench
39   Author: PRP
40   */
41
42#include "systemc.h"
43
44SC_MODULE( tb )
45{
46        SC_HAS_PROCESS( tb );
47
48        sc_in_clk clk;
49
50        // Output Reset Port
51        sc_signal<bool>& reset_sig;
52
53        // Output Data Ports
54	sc_signal<int>& i1;
55	sc_signal<int>& i2;
56	sc_signal<int>& i3;
57	sc_signal<int>& i4;
58	sc_signal<int>& i5;
59
60        // Output Control Ports
61	sc_signal<bool>& cont1;
62	sc_signal<bool>& cont2;
63	sc_signal<bool>& cont3;
64
65        // Input Data Ports
66	const sc_signal<int>& o1;
67	const sc_signal<int>& o2;
68	const sc_signal<int>& o3;
69	const sc_signal<int>& o4;
70	const sc_signal<int>& o5;
71
72	// Constructor
73	tb (
74        sc_module_name NAME,
75	sc_clock& CLK,
76
77        sc_signal<bool>& RESET_SIG,
78
79	sc_signal<int>& I1,
80	sc_signal<int>& I2,
81	sc_signal<int>& I3,
82	sc_signal<int>& I4,
83	sc_signal<int>& I5,
84
85	sc_signal<bool>& CONT1,
86	sc_signal<bool>& CONT2,
87	sc_signal<bool>& CONT3,
88
89	const sc_signal<int>& O1,
90	const sc_signal<int>& O2,
91	const sc_signal<int>& O3,
92	const sc_signal<int>& O4,
93	const sc_signal<int>& O5)
94	  : reset_sig(RESET_SIG), i1(I1),  i2(I2),
95	    i3(I3),  i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
96	    cont3 (CONT3), o1(O1),  o2(O2),  o3(O3),  o4(O4),  o5(O5)
97        {
98	  clk(CLK);
99          SC_CTHREAD( entry, clk.pos() );
100	}
101
102  void entry();
103};
104