test.h revision 12855:588919e0e4aa 
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6  Accellera licenses this file to you under the Apache License, Version 2.0
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10    http://www.apache.org/licenses/LICENSE-2.0
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19
20/*****************************************************************************
21
22  test.h --
23
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32
33      Name, Affiliation, Date:
34  Description of Modification:
35
36 *****************************************************************************/
37
38/* Common interface file for test cases
39   Author: PRP
40   */
41
42#include "systemc.h"
43
44SC_MODULE( t )
45{
46        SC_HAS_PROCESS( t );
47
48        sc_in_clk clk;
49
50        // Input Reset Port
51        const sc_signal<bool>& reset_sig;
52
53        // Input Data Ports
54	const sc_signal<int>& i1;
55	const sc_signal<int>& i2;
56	const sc_signal<int>& i3;
57	const sc_signal<int>& i4;
58	const sc_signal<int>& i5;
59
60        // Input Control Ports
61	const sc_signal<bool>& cont1;
62	const sc_signal<bool>& cont2;
63	const sc_signal<bool>& cont3;
64
65        // Output Data Ports
66	sc_signal<int>& o1;
67	sc_signal<int>& o2;
68	sc_signal<int>& o3;
69	sc_signal<int>& o4;
70	sc_signal<int>& o5;
71
72	// Constructor
73	t (
74        sc_module_name NAME,
75	sc_clock& CLK,
76
77        const sc_signal<bool>& RESET_SIG,
78
79	const sc_signal<int>& I1,
80	const sc_signal<int>& I2,
81	const sc_signal<int>& I3,
82	const sc_signal<int>& I4,
83	const sc_signal<int>& I5,
84
85	const sc_signal<bool>& CONT1,
86	const sc_signal<bool>& CONT2,
87	const sc_signal<bool>& CONT3,
88
89	sc_signal<int>& O1,
90	sc_signal<int>& O2,
91	sc_signal<int>& O3,
92	sc_signal<int>& O4,
93	sc_signal<int>& O5)
94	  : reset_sig(RESET_SIG), i1(I1),  i2(I2),
95	    i3(I3),  i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
96	    cont3 (CONT3), o1(O1),  o2(O2),  o3(O3),  o4(O4),  o5(O5)
97        {
98	  clk (CLK);
99          SC_CTHREAD( entry, clk.pos() );
100	  reset_signal_is(reset_sig,true);
101	}
102
103  void entry();
104};
105