gcd.cpp revision 12855:588919e0e4aa
1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20/***************************************************************************** 21 22 gcd.cpp -- 23 24 Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 25 26 *****************************************************************************/ 27 28/***************************************************************************** 29 30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 31 changes you are making here. 32 33 Name, Affiliation, Date: 34 Description of Modification: 35 36 *****************************************************************************/ 37 38#include "systemc.h" 39 40SC_MODULE( gcd_cc ) 41{ 42 SC_HAS_PROCESS( gcd_cc ); 43 44 sc_in_clk clk; 45 46 const sc_signal<bool>& reset; 47 const sc_signal<unsigned>& a; 48 const sc_signal<unsigned>& b; 49 sc_signal<unsigned>& c; 50 sc_signal<bool>& ready; 51 52 gcd_cc( sc_module_name NAME, 53 sc_clock& CLK, 54 const sc_signal<bool>& RESET, 55 const sc_signal<unsigned>& A, 56 const sc_signal<unsigned>& B, 57 sc_signal<unsigned>& C, 58 sc_signal<bool>& READY ) 59 : 60 reset(RESET), 61 a(A), 62 b(B), 63 c(C), 64 ready(READY) 65 { 66 clk( CLK ); 67 SC_CTHREAD( entry, clk.pos() ); 68 reset_signal_is(reset,true); 69 } 70 71 void entry(); 72}; 73 74void 75gcd_cc::entry() 76{ 77 unsigned tmp_a; 78 wait(); // Note that this wait() is required, otherwise, 79 // the reset is wrong! This is a problem with BC, 80 // not our frontend. 81 82 while (true) { 83 unsigned tmp_b; 84 85 c = tmp_a; 86 ready = true; 87 wait(); 88 89 tmp_a = a; 90 tmp_b = b; 91 ready = false; 92 wait(); 93 94 while (tmp_b != 0) { 95 96 unsigned tmp_c = tmp_a; 97 tmp_a = tmp_b; 98 wait(); 99 100 while (tmp_c >= tmp_b) { 101 tmp_c = tmp_c - tmp_b; 102 wait(); 103 } 104 105 tmp_b = tmp_c; 106 wait(); 107 } 108 } 109} 110 111int sc_main(int argc, char* argv[] ) 112{ 113 return 0; 114} 115