tb.h revision 12855:588919e0e4aa 
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2
3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4  more contributor license agreements.  See the NOTICE file distributed
5  with this work for additional information regarding copyright ownership.
6  Accellera licenses this file to you under the Apache License, Version 2.0
7  (the "License"); you may not use this file except in compliance with the
8  License.  You may obtain a copy of the License at
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10    http://www.apache.org/licenses/LICENSE-2.0
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12  Unless required by applicable law or agreed to in writing, software
13  distributed under the License is distributed on an "AS IS" BASIS,
14  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15  implied.  See the License for the specific language governing
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19
20/*****************************************************************************
21
22  tb.h --
23
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32
33      Name, Affiliation, Date:
34  Description of Modification:
35
36 *****************************************************************************/
37
38/* Common interface file for test bench
39   Author: PRP
40   */
41
42SC_MODULE( tb )
43{
44    SC_HAS_PROCESS( tb );
45
46    sc_in_clk clk;
47
48        // Output Reset Port
49        sc_signal<bool>& reset_sig;
50
51        // Output Data Ports
52	sc_signal<int>& i1;
53	sc_signal<int>& i2;
54	sc_signal<int>& i3;
55	sc_signal<int>& i4;
56	sc_signal<int>& i5;
57
58        // Output Control Ports
59	sc_signal<bool>& cont1;
60	sc_signal<bool>& cont2;
61	sc_signal<bool>& cont3;
62
63        // Input Data Ports
64	const sc_signal<int>& o1;
65	const sc_signal<int>& o2;
66	const sc_signal<int>& o3;
67	const sc_signal<int>& o4;
68	const sc_signal<int>& o5;
69
70	// Constructor
71	tb (
72        sc_module_name NAME,
73	sc_clock& CLK,
74
75        sc_signal<bool>& RESET_SIG,
76
77	sc_signal<int>& I1,
78	sc_signal<int>& I2,
79	sc_signal<int>& I3,
80	sc_signal<int>& I4,
81	sc_signal<int>& I5,
82
83	sc_signal<bool>& CONT1,
84	sc_signal<bool>& CONT2,
85	sc_signal<bool>& CONT3,
86
87	const sc_signal<int>& O1,
88	const sc_signal<int>& O2,
89	const sc_signal<int>& O3,
90	const sc_signal<int>& O4,
91	const sc_signal<int>& O5)
92	  : reset_sig(RESET_SIG), i1(I1),  i2(I2),
93	    i3(I3),  i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
94	    cont3 (CONT3), o1(O1),  o2(O2),  o3(O3),  o4(O4),  o5(O5)
95        {
96	  clk(CLK);
97            SC_CTHREAD( entry, clk.pos() );
98	}
99
100  void entry();
101};
102